Low-power digital systems based on adiabatic-switching principles

Athas, W.C.; Svensson, Lars; Koller, Jeff; Tzartzanis, N.; Chou, E.Y.

doi:10.1109/92.335009

Cited by 497 publications

(221 citation statements)

References 10 publications

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“…E DISS also depends upon the charging time T, If T>>2RC then energy dissipation will be smaller than the conventional CMOS [6]. The energy stored at output can be retrieved by the reversing the current source direction during discharging process instead of dissipation in NMOS network.…”

Section: Dissipation Mechanisms In Adiabatic Logic Circuitsmentioning

confidence: 99%

“…But here constant voltage source is replaced with the constant current source to charge and discharge the output load capacitance. Here R is on resistance of the PMOS network, C L is the load capacitance [6]. Energy dissipation in resistance R is [1] Since E DISS depends upon R, so by reducing the on Resistance of PMOS network the energy dissipation can be minimized.…”

Section: Fig 6: Equivalent Circuit For Charge Recovery Process In Admentioning

confidence: 99%

“…The energy stored at output can be retrieved by the reversing the current source direction during discharging process instead of dissipation in NMOS network. Hence adiabatic switching technique offers the less energy dissipation in PMOS network and reuses the stored energy in the output load capacitance by reversing the current source direction [6,7].…”

Section: Dissipation Mechanisms In Adiabatic Logic Circuitsmentioning

confidence: 99%

See 2 more Smart Citations

Performance Analysis of Energy Efficient and Charge Recovery Adiabatic Techniques for Low Power Design

Yasoda¹

2013

IOSRJEN

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-The power consumption of the electronic devices can be reduced by adopting different design styles.Adiabatic logic style is said to be an attractive solution for such low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and some of energy stored at load capacitance can be recycled instead of dissipated as heat. In analysis, two logic families, ECRL(Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) are compared with conventional CMOS logic for inverter and 2:1 multiplexer circuits. The proposed technique has less power dissipation when compared to the conventional CMOS design style.

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Section: Dissipation Mechanisms In Adiabatic Logic Circuitsmentioning

confidence: 99%

Section: Fig 6: Equivalent Circuit For Charge Recovery Process In Admentioning

confidence: 99%

Section: Dissipation Mechanisms In Adiabatic Logic Circuitsmentioning

confidence: 99%

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Performance Analysis of Energy Efficient and Charge Recovery Adiabatic Techniques for Low Power Design

Yasoda¹

2013

IOSRJEN

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“…As a result, the DPA and DEMA attacks are a bit difficult to avoid. Hence, our approach here is to design secure logic with low peak current transition and low energy consumption by exploiting an adiabatic switch principle [9]. In recent, few papers of secure adiabatic logic have been published which referred to this work, such as SAL [10], and SyAL [11].…”

Section: Introductionmentioning

confidence: 99%

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

Monteiro¹,

Takahashi²,

Sekine³

2013

IJMO

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Abstract-The bit-parallel multiplier over Galois filed arithmetic algorithm and the circuit architecture have been widely studied and implemented in cryptosystem. In this paper, we implement the proposed secure and low-power dual-rail adiabatic logic circuit into the bit-parallel cellular multiplier over GF(2 4 ). The full custom design of the layout has been designed in cadence virtuoso IC6.1 with the chip size of 172×155 m 2 , and the post-layout cyclical power consumption of 14pJ at 12.5MHz using 0.18μm CMOS technology has achieved; while, the well-known conventional TDPL logic in our work using the same technology occupied 183×m 2 of the chip size and 123pJ per cycle. The thoroughly investigation results define that our proposed logic improve energy reduction and the circuit immunity to side-channel attack in the low frequency application, whereas, the TDPL shows the better security performance at high frequency range.Index Terms-Bit-parallel multiplier, adiabatic, low-power, side channel attack, cryptography.

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“…Many researchers have studied this issue in recent years. [3][4][5][6][7][8][9][10][11][12][13][14][15] However, the operational constraint that the output signal should track the power-clock's slow-ramping behavior to accomplish the charging and discharging processes creates a major difficulty in the circuit design. Furthermore, the input signal should be valid when the local output tracks the rising and falling behavior of the power-clock.…”

Section: Resultsmentioning

confidence: 99%

Analysis of power-clocked CMOS with application to the design of energy-recovery circuits

Pedram

Wu²

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

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Low-power digital systems based on adiabatic-switching principles

Cited by 497 publications

References 10 publications

Performance Analysis of Energy Efficient and Charge Recovery Adiabatic Techniques for Low Power Design

Performance Analysis of Energy Efficient and Charge Recovery Adiabatic Techniques for Low Power Design

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

Analysis of power-clocked CMOS with application to the design of energy-recovery circuits

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