Low Power Design of a Two Bit Mangitude Comparator for High Speed Operation

Hasan, Mehedi; Saha, Uttam Kumar; Hossain, Muhammad Saddam; Biswas, Parag; Hossein, Md. Jobayer; Dipto, Md. Ashik Zafar

doi:10.1109/iccci.2019.8822197

Cited by 16 publications

(1 citation statement)

References 13 publications

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“…Ripple Carry Adder (RCA) based on 1-full adder is the basic technique for implementation of wide adders [20][21]. However, propagation delay obtained using RCA in long carry chains in quite high for which it became quite impractical to use RCA in high performance devices [22][23]. In order to solve the carry propagation delay in long carry chains, several Parallel-Prefix Adder topologies have been developed [24].…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

Hasan¹,

Islam²,

Ahmed³

2019

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Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.

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