Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

Hasan, Mehedi; Islam, Moumita Sadia; Ahmed, Muhtasim Rafid

doi:10.11648/j.cssp.20190802.16

Cited by 11 publications

(12 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To overcome this, parallel adder methodologies have evolved among which CLA is quite popular. The carry-generation circuit of 4-bit CLA in [4] is exactly similar to the carry-generation circuit of conventional 4-bit CLA in Fig. 2.…”

Section: Simulation Results Analysis and Comparisonmentioning

confidence: 87%

“…Now, using equations (4), ( 5), ( 6) and ( 7), switch level (transistor level) CLA circuits (for C 1 , C 2 , C 3 and C 4 ) in Fig. 1 have been expressed in reference [4,[11][12][13]. Conventional CLA circuits for computing carry-out terms have been represented by Fig.…”

Section: Conventional 4-bit Cla Process In Static Cmos Logicmentioning

confidence: 99%

“…In the traditional way of implementing wide adder in Ripple Carry Adder (RCA) style, computation in one stage needs to wait for the carry-out bit from the previous stage [3]. Among high-speed wide adder topologies, the CLA process prevails dominant as the delay occurred due to carry propagation is reduced by computing several stages in parallel [4]. Architecture of 4-bit CLA process plays an important role in wide adder design since 4-bit adders are used as fundamental units [5].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Hasan

Siddique

Mondol

et al. 2020

IJEEI

Self Cite

View full text Add to dashboard Cite

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.

show abstract

Section: Simulation Results Analysis and Comparisonmentioning

confidence: 87%

Section: Conventional 4-bit Cla Process In Static Cmos Logicmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Hasan

Siddique

Mondol

et al. 2020

IJEEI

Self Cite

View full text Add to dashboard Cite

show abstract

“…Rather than using static CMOS logic-based circuits, 4-bit CLA cells in Refs 22. 25 used hybrid logic-based circuits.…”

mentioning

confidence: 99%

“…By using this approach, the number of transistors could be reduced and several performance parameters could be improved. CLA cells in Refs 22. 23 used hybrid AND and XOR gates in Refs.…”

mentioning

confidence: 99%

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

Hasan

Chowdhury

Faruqe

et al. 2023

Engineering Reports

View full text Add to dashboard Cite

This research aims to fill up the research gap in energy‐efficient transistor‐level wide word‐length carry circuit generator by using ripple carry (RC) and carry look‐ahead (CLA) method‐based hybrid 4‐bit carry generation process for wide word‐length carry‐select adder (CSLA). Compared to the existing 4‐bit CLA architectures, the proposed 4‐bit RC‐CLA method‐based hybrid 4‐bit carry generator showed performance improvement in terms of power and power delay product (PDP). Later, the 4‐bit carry architectures (existing and proposed) were used as a base to implement 16‐bit carry select adder (CSA) in order to investigate and compare the effect of using the proposed hybrid RC‐CLA based 4‐bit carry generator in large structures. Unlike 4‐bit operation, the proposed design displayed the best performance in power and PDP for 16‐bit CSA extension, which proves its effectiveness in wide word‐length adder structures.

show abstract

Design of High Speed BCD Adder Using CMOS Technology

Share,

Zghoul,

Al-Khaleel

et al. 2023

IEEE Access

View full text Add to dashboard Cite

Decimal arithmetic gains its importance in different applications in the fields of finance and scientific applications. The approach of running decimal arithmetic over binary hardware requires conversions from decimal to binary and from binary to decimal. These conversions produce inexact results that impose financial losses for companies. Therefore, the need for decimal hardware is of high importance. This work proposes decimal addition circuits and presents their realization in complementary metal-oxide semiconductor (CMOS) technology. LTSPICE SPICE simulator software is used to simulate and verify the functionality of the proposed circuits. The circuits are simulated using 45nm, 65nm, and 180nm technologies and compared against existing works in the literature. Due to the lack of existing work in literature and for purpose of comparison, this work also designed five different BCD adders using different existing binary adders in literature. The experimental results show that proposed decimal adder achieves better performance comparing to the other works. For example, for 3-digit operands, the proposed adder shows a power delay product (PDP), in femtojoule (fJ), of 13.88

show abstract

Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

Cited by 11 publications

References 31 publications

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

Design of High Speed BCD Adder Using CMOS Technology

Contact Info

Product

Resources

About