Low Power Decompressor and PRPG with Constant Value Broadcast

Filipek, Michal; Fukui, Yoshiaki; Iwata, Hiroyuki; Mrugalski, Grzegorz; Rajski, J.; Takakura, M.; Tyszer, Jerzy

doi:10.1109/ats.2011.47

Cited by 17 publications

(17 citation statements)

References 15 publications

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“…This paper is the next evolutionary step in the process of developing low power test compression schemes that deploy a group scan gating of [6] (also referred to as a fork scheme). We will demonstrate that, in addition to power consumption, pattern counts (and thus test time) can also be reduced if one decides to diligently re-architect an input scan gating logic.…”

Section: International Test Conferencementioning

confidence: 99%

“…In particular, the EDT-based compression [4] relies on a poweraware scan controller, which itself operates as a linear decompressor gating-off scan chains in a per pattern manner based on encoded test data. It appears [6] that in many designs a simple broadcasting of a constant value to predetermined groups of scan chains can replace the technique of [4].…”

Section: Introductionmentioning

confidence: 97%

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Low Power Test Compression with Programmable Broadcast-Based Control

Milewski

Mrugalski

Rajski

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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This paper introduces a low-power test compression scheme that can also be used in a conventional BIST environment. The key contribution is an observation that simple broadcasting of a constant value to predetermined subsets of scan chains allows visible reductions of both toggling rates and pattern counts provided these subsets can be regrouped when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications of the existing scan gating logic, its synergistic use with test compression algorithms yields a low scan load switching activity, reduced test time, and less intensive traffic of control data. Consequently, the proposed scheme helps to resolve problems related to test power dissipation and elevated test durations.

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Section: International Test Conferencementioning

confidence: 99%

Section: Introductionmentioning

confidence: 97%

Low Power Test Compression with Programmable Broadcast-Based Control

Milewski

Mrugalski

Rajski

et al. 2014

2014 IEEE 23rd Asian Test Symposium

Self Cite

View full text Add to dashboard Cite

show abstract

“…The approaches proposed in [5,6] insert control logics between scan chain inputs and random test pattern generator to reduce the toggle rate of test stimulus bits. M. Filipek et al propose a method that delivers constant values into the specified proportion of scan-chains at a time [7]. However, these methods could decrease test coverage for a given test length.…”

Section: Introductionmentioning

confidence: 99%

Low power logic BIST with high test effectiveness

Wang

Liu

Cai

et al. 2013

IEICE Electron. Express

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Excessive test power has been a serious concern in BIST techniques. Shift power consumption can be significantly reduced by increasing the correlation among adjacent test data bits. However, this method may cause fault coverage loss. This paper presents a novel low power BIST scheme that reduces toggle probability of the scan input data while only shifting out part of capture responses for fault analysis and using the rest of capture responses as new test data. Using part of capture responses as test data can improve uniform distribution of 1 s and 0 s in test stimulus bits and thus result in high test effectiveness. Experimental results on larger benchmark circuits of ISCSAS89 and ITC99 show that the proposed strategy can reduce significantly test power while suppressing test coverage loss.

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“…To improve this technique, the approach in [17] clusters the scan chains into several groups and achieves more significant shift power reduction by limiting scan shift to a portion of groups with mask logics during scan shift. The researchers in [18,23,24] [19]. However, these methods may cause test coverage loss for a given test length.…”

Section: Introductionmentioning

confidence: 99%

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Wang¹,

Cai²,

Xiang³

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

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Low Power Decompressor and PRPG with Constant Value Broadcast

Cited by 17 publications

References 15 publications

Low Power Test Compression with Programmable Broadcast-Based Control

Low Power Test Compression with Programmable Broadcast-Based Control

Low power logic BIST with high test effectiveness

Reducing Test Power and Improving Test Effectiveness for Logic BIST

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