Low power logic BIST with high test effectiveness

Abstract

Excessive test power has been a serious concern in BIST techniques. Shift power consumption can be significantly reduced by increasing the correlation among adjacent test data bits. However, this method may cause fault coverage loss. This paper presents a novel low power BIST scheme that reduces toggle probability of the scan input data while only shifting out part of capture responses for fault analysis and using the rest of capture responses as new test data. Using part of capture responses as test data can improve uniform distribution of 1 s and 0 s in test stimulus bits and thus result in high test effectiveness. Experimental results on larger benchmark circuits of ISCSAS89 and ITC99 show that the proposed strategy can reduce significantly test power while suppressing test coverage loss.

Time multiplexed LBIST for in-field testing of automotive AI accelerators

“…This results in increased test time. Moreover, due to lower correlation among successive pseudorandom patterns, there is increased shift power that causes excessive heat dissipation for device under test (DUT) [15]. Also, excessive peak power during the test increases the required current flow through the DUT, which may damage DUT due to electromigration [16].…”

Reconfigurable scan architecture for test power and data volume reduction

“…Because these designs are complicated, the amount of test data required has also increased significantly, leading to an increase in the test time and costs. Test power dissipation has also emerged as a serious problem because power consumption in the test mode is significantly higher than that in the normal mode [1,2,3]; moreover, excessive test power consumption results in serious problems such as IR drops, yield losses, and over-testing [4,5]. To resolve these problems, we propose various scan-based test methods to reduce test power consumption.…”