Low-Power Binary Neuron Circuit With Adjustable Threshold for Binary Neural Networks Using NAND Flash Memory

Abstract

Recent studies have demonstrated that binary neural networks (BNN) could achieve a satisfying inference accuracy on representative image datasets. BNN conducts XNOR and bit-counting operations instead of high-precision vector-matrix multiplication (VMM), significantly reducing the memory storage. In this work, an analog bit-counting scheme is proposed to decrease the burden of neuron circuits with a synaptic architecture utilizing NAND flash memory. A novel binary neuron circuit with a double-gate positive feedback (PF) device is demonstrated to replace the sense amplifier, adder, and comparator, thereby reducing the burden of the complementary metal-oxide semiconductor (CMOS) circuits and power consumption. By using the double-gate PF device, the threshold voltage of the neuron circuits can be adaptively matched to the threshold value in the algorithms eliminating the accuracy degradation introduced by the process variation. Thanks to the super-steep SS characteristics of the PF device, the proposed neuron circuit with the PF device has an off-state current of 1 pA, representing 10 5 times improvement compared to the neuron circuit with a conventional metal-oxide-semiconductor field effect transistor (MOSFET) device. A system simulation of a hardware-based BNN shows that the lowvariance conductance distribution (8.4 %) of the synaptic device and the adjustable threshold of the neuron circuit implement a highly efficient BNN with a high inference accuracy.

Neural oscillation of single silicon nanowire neuron device with no external bias voltage

“…External bias lines are indispensable for tuning spiking voltages in neuron devices with independent double-gate field-effect transistors 14 ; such devices have high energy consumption (9.5 × 10 −13 J) and a low firing frequency (~ 300 Hz). Neuron circuits using a positive feedback mechanism 15 – 17 reported by other research groups require more than five components and two external bias lines to implement their integration and firing operations. In addition, these neuron circuits 15 , 16 consume substantial energy (2.5 × 10 −13 J and 6.2 × 10 −13 J) while having low firing frequencies (~ 300 Hz and ~ 30 kHz).…”

“…However, most artificial neurons demand dozens of transistors to emulate biological neuron operation, in turn, greatly sacrificing the advances in integration density and power consumption 4 , 11 – 13 . To improve the integration capabilities, diverse neuron devices and circuits have been widely researched: NPN devices with double gates on a silicon-on-insulator (SOI) 14 , feedback field-effect transistors (FBFETs) 15 – 17 , skyrmion devices based on magnetic tunnel junction 18 , resistive random access memory (ReRAM) 19 , conductive bridge random access memory (CBRAM) 20 , ferroelectric field-effect transistors (FeFET) 21 , 22 and phase-change devices 23 . However, these neuron devices and circuits require numerous component transistors and consume considerable energy to operate in addition to external bias voltages necessary for tuning firing voltages.…”

Water-induced dual ultrahigh mobilities over 400 cm2 V−1 s−1 in 2D MoS2 transistors for ultralow-voltage operation and photoelectric synapse perception

“…Such results show that different degrees of memory can be effectively realized through the simple linear rules, indicating that our device could provide a fresh perspective for future bionic storage. [33][34][35] In a nervous system, the postsynaptic current (PSC) response depends on not only the stimulus amplitude but also the duration time of the stimulus. 30 As shown in Fig.…”

“…These interesting memory behaviors with adjustable rates are very meaningful for the next-generation bionic storage systems that facilitate memory optimization. [34][35][36] In a postsynaptic neuron, EPSCs and IPSCs are complementary processes with close cooperation, which underlie the essential features of neuronal transmission for learning and memory events. 31 Fig.…”

“…These interesting memory behaviors with adjustable rates are very meaningful for the next-generation bionic storage systems that facilitate memory optimization. 34–36…”