Low Power Area Efficient VLSI Architectures for Shift Register Using Explicit Pulse Triggered Flip Flop Based on Signal Feed-Through Scheme

Sujita, B.; Vasavi, K. Padma

doi:10.9790/4200-0605013341

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2018

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“…A new pattern generation technique is implemented for low power using a modified conventional LFSR, in which shift registers may be implemented by using pulsed latches and flip-flops. However, shift register implemented by pulsed latches have power and area problems .So, flip flops are preferred over pulsed latches [5].…”

Section: Introductionmentioning

confidence: 99%

BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications

Parvathi¹,

Vasantha²,

Prasad³

2018

IJRES

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One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.

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Section: Introductionmentioning

confidence: 99%

BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications

Parvathi¹,

Vasantha²,

Prasad³

2018

IJRES

View full text Add to dashboard Cite

show abstract

Low Power Area Efficient VLSI Architectures for Shift Register Using Explicit Pulse Triggered Flip Flop Based on Signal Feed-Through Scheme

Abstract: A register that is designed to allow the bits of its contents to be moved to

Cited by 1 publication

References 4 publications

BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications

BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications

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