Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks

Abstract

We propose a novel architecture for low-power area-efficient large-scale IP lookup engines. The proposed architecture greatly increases memory efficiency by storing associations between IP addresses and their output rules instead of storing these data themselves. The rules can be determined by simple hardware using a few associations read from SRAMs, eliminating a power-hungry search of input addresses in TCAMs. The proposed hardware that stores 100,000 144-bit entries is evaluated under TSMC 65nm CMOS technology. The dynamic power dissipation and the area of the proposed hardware are 4.6% and 30.6% of a traditional TCAM, respectively while maintaining comparable throughput.