Low-power area-efficient high-speed I/O circuit techniques

Abstract

We present a 4-Gb/s I/O circuit that fits in 0.1-mm 2 of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-m CMOS technology. Swing reduction is used in an input-multiplexed transmitter to provide most of the speed advantage of an output-multiplexed architecture with significantly lower power and area. A delay-locked loop (DLL) using a supply-regulated inverter delay line gives very low jitter at a fraction of the power of a source-coupled delay line-based DLL. Receiver capacitive offset trimming decreases the minimum resolvable swing to 8 mV, greatly reducing the transmission energy without affecting the performance of the receive amplifier. These circuit techniques enable a high level of I/O integration to relieve the pin bandwidth bottleneck of modern VLSI chips.

A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects

“…While the input-referred offset can be compensated by increasing the total area of the sense amplifier [30], this reduces sensitivity by increasing input capacitance and also results in higher power consumption. Thus, in order to minimize the input-referred offset while still using relatively small devices, a capacitive trimming offset correction technique is used [31]. As shown in Fig.…”

Pulsenet - A Parallel Flash Sampler and Digital Processor IC for Optical SETI

“…, whose outputs drive a second stage of reduced-size SAs (improving gain and reducing hysteresis), followed by RS latches. The SA (see [2] and references therein) is a simple clocked, regenerative, differential amplifier shown in Fig. 6.…”

On-chip data communication : analysis, optimization and circuit design

“…This transistor prevents that the output of the SA becomes floating when the input signal changes polarity after a decision has already been made [164]. The other two dotted transistors in Figure 9.1 are additional reset transistors that reset the Di nodes [85,158,166,172]. They improve operation at high common-mode input voltages (as discussed later) and also significantly reduce the hysteresis (or memory effect) of the comparator.…”

“…Especially voltage-mode SA's, as shown in Figure 9.1 on the next page, have become quite popular [158,[163][164][165][166][167]. This circuit is also often referred to as a 'StrongARM' latch and a few variants are patented by Digital Equipment Corporation (DEC) [168].…”

“…Sense amplifiers (SA) are hence widely applied in e.g. logic, memories, I/O data receivers [158], A/D converters [159][160][161][162], and more recently also in on-chip transceivers [20,33,61,67,69,72,77,84,85,121,124].…”