A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects

Abstract

Abstract-Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm 2 .Index Terms-Clock and data recovery, equalization, laser driver, optical interconnects, optical receiver, serial transceiver, VCSEL.

A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing

“…Transmitters/Receivers: Following the methodology in [12,24] and assuming a conservative 100 fF capacitance for driver plus modulator, as well as a 2.4 fF photodetector capacitance (as reported in [6]), we estimate 40.5 µW/Gb/s and 147 µW/Gb/s power at 32 nm technology node for a single transmitter and receiver, respectively. This corresponds to 1.3 mW transmitter power and 4.7 mW receiver power at 32 Gb/s optical data rate.…”

Design of a scalable nanophotonic interconnect for future multicores

“…VCSELs allow for direct modulation of the carrier signal, but consume more power and area and are harder to integrate with III-V semiconductors [15]. Microring resonators and MZ modulators use indirect modulator (external laser) which has the advantage that the power of the laser is not accounted in the total on-chip power budget.…”

“…Therefore, in our design we utilize 64 wavelengths and extensively reuse these wavelengths to achieve scalable bandwidth. 1.10 0.03 90-nm CMOS [15] 3.63 0.07 SiGe Bi-CMOS [18] 9.20 1.07…”

17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnection

“…Many studies have focused on developing high-speed, low-power transceivers for optical interconnection [1][2][3][4][5][6][7]. The loss of the waveguide is significantly lower than that of the metal line; therefore, high-speed data transmissions that exceed the metal line transmission limit can be achieved.…”

“…However, optical waveform degradation becomes a serious issue as the data rate increases because of parasitic capacitance and nonlinear response of the vertical-cavity surface-emitting laser (VCSEL). In some studies, a pre-emphasis technique incorporating a finite impulse response (FIR) filter used in the electrical interconnection was applied to the VCSEL transmitter in order to suppress waveform degradation due to the parasitic capacitance [4][5][6]. However, because the FIR filter is a linear system and the VCSEL response is nonlinear, this technique cannot suppress waveform degradation due to the nonlinear VCSEL response.…”