Low power architecture design and hardware implementations of deblocking filter in H.264/AVC

Chung, Hua-chang; Chen, Zong-Yi; Chang, Pao-Chi

doi:10.1109/tce.2011.5955212

Cited by 12 publications

(2 citation statements)

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“…The main objective of this work is to adopt the advantages of previously proposed MBISR [15, 16, 19, 20] and mitigating the limitations, while keeping a hawk eye on trade‐offs. The advantages and some checks are as described below:…”

Section: Advantages and Some Checks Of Proposed Algorithmmentioning

confidence: 99%

“…Several other galloping bit/patterns-based algorithms were also developed to enhance the fault coverage of targeted fault classes [11,12]. The modified galloping pattern-based and checkerboard algorithms also provide good diagnosis speed and fault coverage [13][14][15][16][17][18]. In these designs, the MBISR hardware consists of three main modules i.e.…”

Section: Introductionmentioning

confidence: 99%

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Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

Pundir

2019

IET Circuits, Devices & Systems

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The article presents a new augmented and improved MMBISR for SRAM using hybrid redundancy analysis (HRA). The presented algorithm is the augmented version of essential spare pivoting (ESP) and local repair most (LRM). The algorithm proposes the best solution by providing optimised set of row and column combination which were suitable for the repairing process. In the proposed redundancy analysis (RA) algorithm, the fault dictionary can be updated or fixed concurrently, according to MBIST needs and supplied control signals. The row and column pivots and repair requests are also serviced according to precedency list prepared by the comparing actions. The comparative analysis with LRM and ESP-RA algorithms shows that the proposed algorithm has reduced complexity and tracing time in terms of implementation and in terms of finding row and column pivots. For the implementation, a MBISR hardware structure is designed and tested using suitable VHDL descriptions that were targeted for Virtex-5, xc5vlx30 FPGA. The results were also justified that the proposed algorithm is quite effective as the repair rate is increased up to 4% compared to the ESP. However, some nominal area penalty is observed as compared to ESP.

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