Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs

Abstract

Abstract-This paper focuses on low-power and low-slew clock network design and analysis for through-silicon via (TSV) based three dimensional stacked ICs (3D ICs). First, we investigate the impact of the TSV count and the TSV RC parasitics on clock power consumption. Several techniques are introduced to reduce the clock power consumption and slew of the 3D clock distribution network. We analyze how these design factors affect the overall wirelength, clock power, slew, and skew in 3D clock network design. Second, we develop a two-step 3D clock tree synthesis method: 1) 3D abstract tree generation based on the three dimensional method of means and medians (3D-MMM) algorithm; 2) buffering and embedding based on the slew-aware deferred-merge buffering and embedding (sDMBE) algorithm. We also extend the 3D-MMM method (3D-MMM-ext) to determine the optimal number of TSVs to be used in the 3D clock tree so that the overall power consumption is minimized. Related SPICE simulation indicates that: (1) a 3D clock network that uses multiple TSVs significantly reduces the clock power compared with the single-TSV case; (2) as the TSV capacitance increases, the power savings of a multiple-TSV clock network decreases; and (3) our 3D-MMM-ext method finds a close-tooptimal design point in the "TSV count vs. power consumption" tradeoff curve very efficiently.Index Terms-Low-power 3D IC design, 3D clock network, clock slew, through-silicon via (TSV)

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

“…Such high quality clock trees fully utilizing 3D design space can span entire dies as shown in Fig. 1 [7][8][9][10][11][12][13][14]. To safely apply highly optimized 3D clock trees distributed on multiple dies to a main production process of 3D ICs, we need to consider a new 3D process variation issue which is a special item distinguished from the conventional process variation for 2D clock trees.…”

“…For the buffered clock tree designs, 3D clock tree synthesis (CTS) algorithms are studied in the works [7][8][9][10]. Minz, Zhao, and Lim [7] minimize and balance temperature dependent skew by relocating merging points of an initial zero skew clock tree.…”

“…Minz, Zhao, and Lim [7] minimize and balance temperature dependent skew by relocating merging points of an initial zero skew clock tree. They also provided detail analysis to show low power clocking property of the multi-TSV approach compared to the single-TSV approach in the work [8]. Kim and Kim proposed low cost and low power 3D CTS solution while guaranteeing a minimal use of TSVs in the work [9] and Manuscript received Aug. 22, 2011; revised Dec. 1,2011.…”

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration

“…These networks are characterized by large capacitive loads and high-frequency switching. This requires a large amount of power, possibly up to 50% of total power consumption [34].…”

“…Our optimization methodology MoDo is presented in Section III; an experimental investigation is provided in Section IV. Our conclusions on optimizing deadspace for 3D ICs and its benefits are given in Section V. [25]) [19], [20] rarely aligned nonuniform; Thermal ≈ 2 − 40µm may be encouraged low -medium irregular small -medium contigous regions; [7] [8], [9], [27] possibly aligned nonuniform; Power/Ground ≈ 10 − 40µm strongly preferred low irregular small contigous regions; [7], [13], [14], [16] [11], [13], [14], [16] necessarily aligned nonuniform; Clock ≈ 2 − 20µm may be encouraged low irregular small contigous regions; [33] [33], [34] possibly aligned…”