Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising

Sumalatha, M. R.; Naganjaneyulu, P. V.; Prasad, K. Satya

doi:10.1016/j.micpro.2019.102883

Cited by 38 publications

(28 citation statements)

References 11 publications

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“…This described VD-CLA structure can improve by taking a gander at other electronic system performance metrics to seek the best arrangement of attributes intended for a specific denoising application, e.g., mean squared error (MSE), signal-to-noise ratio (SNR), peak signal-to-noise ratio (PSNR), bit error rate (BER), and [25,[36][37][38][39][40][41].…”

Section: Discussionmentioning

confidence: 99%

“…Distributed arithmetic (DA) calculation employs a high request FIR channel FIRF is consolidated with a MAC unit to increase the contribution of coefficients, to move, and after that to include them. However, the delay augments Sumalatha et al [25] A low-power and low-area VLSI implementation of the VD FIRF for ECG signal denoising Low-power and fast FIRF implemented using Vedic multiplier and 16-bit CLA adder for ECG denoising application Doss et al [22] The pipelined architecture for adaptive FIRF design employed the DA algorithm with a highthroughput rate achieved by the updated LUT…”

Section: Literature Reviewmentioning

confidence: 99%

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The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

Sowmya¹,

Chandana²,

Anjana³

2020

Advances in Multidisciplinary Medical Technologies ─ Engineering, Modeling and Findings

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Finite impulse response (FIR) filter implementations abound and play a major part in signal processing applications. The FIR filter (FIRF) delivers several benefits, and there exist many different realizations, such as designs using a system generator, normal FIRF, decimator FIRF, genetic algorithm (GA)-based, and parallelbased, among others. Most architectures utilize more hardware with less efficiency. Moreover, these existing architectures did not concentrate on and explored the applications' characteristics. The FIRF affords several paybacks like (i) computational efficiency in multi-rate frameworks, (ii) manageable linear phase response, and (iii) the desirable numerical ability to accomplish finite precision and fractional arithmetic. The digital multi-standard RFIR filter is implemented in wireless applications to decrease the bit error rate (BER). The discrete FIRF can render efficient designs with low-power consumption and high performance. Earlier, hordes of research articles described different FIRF designs without handling signal denoising with an effective multiplier design. Booth's algorithm performs multiplication by multiplying two signed binary numbers in 2's complement notation. The Booth multiplier (BM) overcomes the reduced area drawback, but it would not work with alternation of zeros and ones since it entails more additions and subtractions [1-3]. This problem is overcome by the modified BM (MBM), which contains half the number of partial product rows. It functions well regarding speed and power consumption. On the other hand, its main shortcoming is sloppy work for negative numbers [4, 5].

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Section: Discussionmentioning

confidence: 99%

Section: Literature Reviewmentioning

confidence: 99%

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

Sowmya¹,

Chandana²,

Anjana³

2020

Advances in Multidisciplinary Medical Technologies ─ Engineering, Modeling and Findings

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“…The estimated delay based on (Gate delay-DG) for Distributed Arithmetic unit of LUT, LUT-less and Int J Elec & Comp Eng ISSN: 2088-8708  Design and implementation of DA FIR filter for bio-inspired computing architecture (B. U. V. Prashanth)1715proposed architecture implementation[22,23] is as shown in the Figure8. Here the delay of the proposed architecture is 14 % (for 8-order filter) and 64.7% (for 140-order filter) less delay in comparison of LUT-less architecture[24,25].…”

mentioning

confidence: 87%

Design and implementation of DA FIR filter for bio-inspired computing architecture

Prashanth

Ahmed

Kounte

2021

IJECE

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This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.

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“…Pada artikel ini akan dikembangkan penggunakan filter IIR pada data sinyal pernapasan EMGdi pernah dilakukan pada [2] dengan membandingkan segi keefektifan filter dengan menggunakan filter FIR. Berdasarkan [3][4] filter FIR mampu menghilangkan noise pada pengaplikasian sinyal ECG karena memiliki properti fasa yang linear dan karakteristik yang stabil serta mampu meningkatkan kecepatan kalkulasi filter sebesar 13,65%. Oleh karena itu, artikel ini akan mencoba mengaplikasikan penelitian [2] dengan menggunakan filter FIR dan melihat apakah keefektifan filter tersebut juga berlaku ketika diaplikasikan pada sinyal EMGdi dengan menggunakan Signal-to-Noise Ratio (SNR), execution time, serta zero-pole diagram kedua filter.…”

Section: Pendahuluanunclassified

Analisis Keefektifan Penggunaan Filter FIR dan IIR pada Sinyal Pernapasan EMGdi dengan Simulasi MATLAB

Leonard

Shabrina²

2020

ULTIMA Computing

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Instrumentasi medis digunakan untuk mendapatkan dan merekam data sinyal dari tubuh pasien salah satunya adalah sinyal pernapasan. Data dari sinyal pernapasan tersebut mampu mendiagnosa kesehatan pernapasan pasien. Dalam memperoleh data sinyal tersebut, terdapat noise yang mengganggu informasi sinyal yang diperlukan. Pada artikel ini, sinyal input akan dilakukan filter dengan dua tipe filter (filter FIR dengan metode window method dan filter IIR dengan pole-zero placement method atau bilinear transformation method) dan dibandingkan keefektifan kedua tipe filter dalam mengurangi atau menghilangkan noise sinyal. Kedua filter memiliki frekuensi cut-off sebesar 50 Hz. Sinyal output menunjukkan bahwa sinyal noise ECG lebih efektif dihilangkan menggunakan filter IIR. Oleh karena itu, filter IIR lebih direkomendasikan digunakan dalam instrumentasi medis karena keefektifan serta penggunaan perangkat keras yang minimum.

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Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising

Cited by 38 publications

References 11 publications

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

Design and implementation of DA FIR filter for bio-inspired computing architecture

Analisis Keefektifan Penggunaan Filter FIR dan IIR pada Sinyal Pernapasan EMGdi dengan Simulasi MATLAB

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