Low power and high testable Finite State Machine synthesis

Pradhan, Sambhu Nath; Choudhury, Priyanka

doi:10.1109/iemcon.2015.7344528

Cited by 7 publications

(2 citation statements)

References 7 publications

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“…By using partition of FSMs, the switching power dissipation can be reduced up to 80% [7]. Reddy et al presented a partitioning‐based state encoding approach target to low power [8]; Pradhan et al proposed a high‐performance method to trade fault coverage with power for FSM synthesis [33]; Klimowicz et al used minimisation method of FSM for low‐power design, which takes possibility of merging other states into account at the stage of minimising internal states [34]. In addition to dynamic power minimisation, leakage power reduction has been also taken into account by some works.…”

Section: Related Workmentioning

confidence: 99%

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

Tao

Zhang

Wang

et al. 2018

IET Computers & Digital Techniques

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As the development of deep-submicron and nano-technology, leakage power minimisation becomes as important as dynamic power reduction in IC design. In order to achieve low-power state assignment for finite-state machine (FSM) synthesis, a multi-population genetic algorithm (MPGA)-based state assignment method is proposed. MPGA consists of an outer-loop and a set of inner-GAs. In MPGA, inner-GA is a local search component for finding low-power state assignment. Selection, crossover and mutation are used to perform variations on individuals. Cost function is defined based on power dissipation formulation of complementary metal oxide semiconductor (CMOS) gate for dynamic power and leakage power estimation. The outer-loop is used to optimise the parameters of inner-genetic algorithm (GA) through population variation schema, intra-specific competition and newborn. Twenty-three FSMs that were commonly used as benchmarks are employed to test the effectiveness of MPGA and compare different state assignment methods. Experimental results show MPGA achieves a significant improvement over the previous publications both on dynamic power and leakage power reduction in most benchmarks.

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Section: Related Workmentioning

confidence: 99%

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

Tao

Zhang

Wang

et al. 2018

IET Computers & Digital Techniques

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“…Due to the area and speed advantages, they act as an excellent alternative to their conventional LUT-based counterparts [7]. In such implementations, a considerable reduction in power consumption is obtained by disabling embedded memory blocks (EMBs) during the idle 2 International Journal of Reconfigurable Computing states [8,9]. The fundamental framework for FSM with input multiplexing (FSMIM) is made in [7] whose prime objective is to shorten the depth of ROM memory.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

Das

Priya

2018

International Journal of Reconfigurable Computing

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The mathematical model for designing a complex digital system is a finite state machine (FSM). Applications such as digital signal processing (DSP) and built-in self-test (BIST) require specific operations to be performed only in the particular instances. Hence, the optimal synthesis of such systems requires a reconfigurable FSM. The objective of this paper is to create a framework for a reconfigurable FSM with input multiplexing and state-based input selection (Reconfigurable FSMIM-S) architecture. The Reconfigurable FSMIM-S architecture is constructed by combining the conventional FSMIM-S architecture and an optimized multiplexer bank (which defines the mode of operation). For this, the descriptions of a set of FSMs are taken for a particular application. The problem of obtaining the required optimized multiplexer bank is transformed into a weighted bipartite graph matching problem where the objective is to iteratively match the description of FSMs in the set with minimal cost. As a solution, an iterative greedy heuristic based Hungarian algorithm is proposed. The experimental results from MCNC FSM benchmarks demonstrate a significant speed improvement by 30.43% as compared with variation-based reconfigurable multiplexer bank (VRMUX) and by 9.14% in comparison with combination-based reconfigurable multiplexer bank (CRMUX) during field programmable gate array (FPGA) implementation.

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Multiple Codes State Assignment and Code Length Reduction for Power Minimization of Finite State Machines

Grzes

2018

Computer Information Systems and Industrial Management

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Low power and high testable Finite State Machine synthesis

Cited by 7 publications

References 7 publications

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

Multiple Codes State Assignment and Code Length Reduction for Power Minimization of Finite State Machines

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