Low Power and High Speed Dadda Multiplier using Carry Select Adder with Binary to Excess-1 Converter

Munawar, Muteen; Khan, T.; Rehman, Muhammad; Shabbir, Zain; Daniel, Kamran; Sheraz, Ahmed; Omer, Muhammad

doi:10.1109/icetst49965.2020.9080739

Cited by 8 publications

(6 citation statements)

References 8 publications

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“…The proposed design is also compared to some recent, closely related works in the literature, i.e., 16,17,43,44,46,47,48,49 , where 49 is an approximate multiplier-based design. It can be seen in Table 6 that our design outperforms these in terms of delay, power consumption, energy efficiency, and transistor count.…”

Section: Simulation Results and Performance Comparisonmentioning

confidence: 99%

“…Therefore, to make a justified comparison, our design is simulated with the same frequencies and technologies. For example, in 17 , TSMC-90 nm technology with a 500 MHz frequency is used, while in 46 TSMC-40 nm technology with a 100 MHz frequency is used, and to make a comparison with these papers, different technologies and frequencies are used correspondingly.…”

Section: Simulation Results and Performance Comparisonmentioning

confidence: 99%

“…As a result, the power consumption and area of the chip were improved. In 17 , the authors modified the carry-select adder (CSA) using a binary to excess-1 (BEC1) converter and used this circuit as a compressor to implement the circuit of the Dadda multiplier, which improved the speed, area, and energy as compared to the traditional CSA-based design. To reduce power and area, an optimized adder with pass transistor logic is used to design a dadda multiplier in 18 , but the output voltage levels are not as strong as in CMOS logic.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Area, Delay, and Energy-Efficient Full Dadda Multiplier

Munawar

Shabbir

Akram

2023

J CIRCUIT SYST COMP

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The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50[Formula: see text]nm, 90[Formula: see text]nm, and 120[Formula: see text]nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33[Formula: see text]GHz. Specifically, the 4-bit circuit of the proposed design in TSMC’s 50[Formula: see text]nm technology consumes 25[Formula: see text]uW of power at 3.33[Formula: see text]GHz with 76[Formula: see text]ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.

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Section: Simulation Results and Performance Comparisonmentioning

confidence: 99%

Section: Simulation Results and Performance Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Area, Delay, and Energy-Efficient Full Dadda Multiplier

Munawar

Shabbir

Akram

2023

J CIRCUIT SYST COMP

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“…Multiplication is one among those operations. Multiplication is one of the main factors which helps in getting high data rates based on its speed of functionality [1]. Now-a-days the technology has been upgrading rapidly, equally the electronic components should also be upgraded in terms of their power, area, speed etc.…”

Section: Introductionmentioning

confidence: 99%

Implementing and Analysing the Performance of Dadda Multiplier on FPGA

Sunkireddy¹,

Thallapally²,

Avula³

et al. 2023

IJRASET

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Multiplication is an arithmetic operation where we will perform some arithmetic operations on the input operands and obtains the final result. Natural multiplication involves partial products generation and adding the obtained partial products to get the final result. But it consumes more power and time if the bit-width increases. Hence, we will use a Dadda Multiplier which results in increasing the execution speed and power efficiency and we will observe the same on FPGA. Hence this arithmetic technique can be used in various error tolerant applications such as image processing, digital processing and FFT.

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“…The squaring operation represents one of the most arithmetic operations in high-speed applications involved cryptography, animation, image compression, fast-Fourier transform (FTT), pattern recognition, adaptive filtering, and others [1][2][3]. Although squaring function is executed by utilizing multipliers such as Booth, Wallace tree, Dadda, or Vedic multiplier, commonly, performing squaring function by multiplication needs recurring addition operations that incur consuming the computing-time and unnecessarily increasing the area of overall design [4][5][6]. Thus, utilizing dedicated squarer circuits can help improve the speed of various applications and enhance the general area of the structure [7].…”

Section: Introductionmentioning

confidence: 99%

Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

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Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of 32-bit floating-point numbers. The paper also offers three architectures for 24-bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12-bit, and 24-bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24-bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with (3*3) VM introduces the lowest area and delay.

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Low Power and High Speed Dadda Multiplier using Carry Select Adder with Binary to Excess-1 Converter

Cited by 8 publications

References 8 publications

Area, Delay, and Energy-Efficient Full Dadda Multiplier

Area, Delay, and Energy-Efficient Full Dadda Multiplier

Implementing and Analysing the Performance of Dadda Multiplier on FPGA

Vedic-Based Squarers with High Performance

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