Low Power and High Speed Sample-and-Hold Circuit

Trivedi, R.

doi:10.1109/mwscas.2006.382096

Cited by 10 publications

(2 citation statements)

References 2 publications

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“…We simulated this circuit with zero-threshold and no hysteresis. Finally, the digital estimation section uses the sample-and-hold [25] and a 3-bit (S=8) binary counter (a few logic gates and three sequential cells) [26]. A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next.…”

Section: Vlsi System Implementationmentioning

confidence: 99%

Upgrading an analog recovery loop for optimized decoding jointly to an increased data rate

Visalli¹

2021

Telecommun Syst

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The maximum likelihood detection theory improves the error rate of a sub-optimal but cheaper, coded symbol recovery loop using oversampling proposed as an alternate solution for the decoding problem without the log-likelihood ratio computation. The former implementation delivers the output data in one-symbol delay, and the required transistor count makes this approach attractive for ultra-low-energy wireless applications. The proposed hardware upgrade includes an analog to digital converter and fixed-point accumulation logic to compute the soft values, replacing a trigger used as a hard detector. This work investigates the soft decoding in the presence of binary and non-binary source symbols. Simulation results show that the soft approach improves the signal-to-noise ratio by 3dB and 2.5 dB when the encoding rates are 1/3 and 2/3.

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Section: Vlsi System Implementationmentioning

confidence: 99%

Upgrading an analog recovery loop for optimized decoding jointly to an increased data rate

Visalli¹

2021

Telecommun Syst

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“…Therefore, an open issue is the design of hardware systems capable of S&H advanced systems. Studies on the use of S&H-β in control systems report relevant results for improving the overall performance [41][42][43][44][45][46]. In this perspective, the construction of low cost general S&H may be a valuable option for obtaining equipment more friendly to the environment while not posing significant financial requirements.…”

Section: The Transfer Functions Of the Sandhmentioning

confidence: 99%

A Review of Sample and Hold Systems and Design of a New Fractional Algorithm

Ortigueira

Machado

2020

Applied Sciences

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Digital systems require sample and hold (S&H) systems to perform the conversion from analog to digital and vice versa. Besides the standard zero and first order holds, we find in the literature other versions, namely the fractional and exponential order holds, involving parameters that can be tuned to produce a superior performance. This paper reviews the fundamental concepts associated with the S&H and proposes a new fractional version. The systems are modeled both in the time and Laplace domains. The new S&H stemming from fractional calculus generalizes these devices. The different S&H systems are compared in the frequency domain and their relationships visualized by means of hierarchical clustering and multidimensional scaling representations. The novel strategy allows a better understanding of the possibilities and limitations of S&H systems.

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