A new high-speed, high-resolution open-loop CMOS sample and hold

Abolhasani, Alireza; Tohidi, Mohammad; Hadidi, Khayrollah; Khoei, Abdollah

doi:10.1007/s10470-013-0158-z

Cited by 8 publications

(5 citation statements)

References 14 publications

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“…However, the charges introduced by switches in a differential topology do not exactly cancel each other because the two input differential signals are not equal to each other. Therefore, charge injection error generates odd harmonics [2]. Further according to the investigation in [12], for low-voltage operations, bulk-effect compensation improves third-order harmonic noticeably which is confirmed by achieved results for the proposed switch in this work, too.…”

Section: Simulation Resultssupporting

confidence: 84%

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Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

Sarafi

A’ain

Abbaszadeh

2015

Circuits Syst Signal Process

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Sampling switches have a dominant role in switched-capacitor circuits and analog-to-digital convertors. Since they act as input gates, their nonlinearities directly degrade the quality of the input signals. The scaling-down trend of CMOS technology and increasing demands for high-speed and power-efficient circuits pose design challenge in high-speed sampling switches for low-voltage applications. To address this issue, an optimized CMOS switch is proposed in this paper consisting of a bootstrapped NMOS switch and a boosted PMOS switch as a transmission gate. By utilizing this technique, the nonlinearity resulting from the threshold voltage variation (body effect) of NMOS switch is mitigated, considerably. To evaluate the proposed switch, it is designed in 0.18 μm CMOS process technology. According to the obtained simulation results, this switch can achieve total harmonic distortion of −78.81 and −62.99 dB in 100 MS/s at V dd = 1 Volt and 50 MS/s at V dd = 0.8 V, respectively.

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Section: Simulation Resultssupporting

confidence: 84%

“…In this work, variable factor is approximated to a linear function of V sb as calculated in Eq. (2).…”

Section: Investigation Of Body Effect As Linear Modelmentioning

confidence: 99%

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

Sarafi

A’ain

Abbaszadeh

2015

Circuits Syst Signal Process

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“…Some techniques have been developed by many researchers to decrease hold error voltage in S/H circuit [12][13][14][15][16][17][18][19][20][21]. Most of them use an additional circuit to decrease the hold error.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…From equation 13it can be known that total hold error consists of two simple parts with a different sign, the width of P-type MOS transistor W P with a coefficient a and width of N-type MOS transistor W N with a coefficient -b. The coefficient a and b is shown in equations (14) and (15), respectively. These equations can now be used to adjust W P and W N properly to achieve zero hold error.…”

Section: Proposed Methodsmentioning

confidence: 99%

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Setiabudi

Tamura

Tanno

2018

International Journal on Advanced Science, Engineering and Information Technology

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Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width W P range of 3 to 35 µm the average W N /W P ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.

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“…This paper has not addressed the electronic implementation of such devices (interested readers can refer to [34][35][36][37][38][39][40] and references therein). Therefore, an open issue is the design of hardware systems capable of S&H advanced systems.…”

Section: The Transfer Functions Of the Sandhmentioning

confidence: 99%

A Review of Sample and Hold Systems and Design of a New Fractional Algorithm

Ortigueira

Machado

2020

Applied Sciences

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Digital systems require sample and hold (S&H) systems to perform the conversion from analog to digital and vice versa. Besides the standard zero and first order holds, we find in the literature other versions, namely the fractional and exponential order holds, involving parameters that can be tuned to produce a superior performance. This paper reviews the fundamental concepts associated with the S&H and proposes a new fractional version. The systems are modeled both in the time and Laplace domains. The new S&H stemming from fractional calculus generalizes these devices. The different S&H systems are compared in the frequency domain and their relationships visualized by means of hierarchical clustering and multidimensional scaling representations. The novel strategy allows a better understanding of the possibilities and limitations of S&H systems.

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A new high-speed, high-resolution open-loop CMOS sample and hold

Cited by 8 publications

References 14 publications

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

A Review of Sample and Hold Systems and Design of a New Fractional Algorithm

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