Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

Toofan, Siroos; Rahmati, A.; Abrishamifar, Adib; Lahiji, G.R.

doi:10.1016/j.mejo.2008.07.073

Cited by 21 publications

(11 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The first reason is to resonate with the total drain capacitance to achieve the desired frequency range. The other reason is to provide high enough impedance to allow a good gain [12]. Furthermore, BJTs require less bias current than MOSFETs for the same amount of the third-order intermodulation.…”

Section: Design Considerationsmentioning

confidence: 99%

A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique

Rastegar¹,

Lim²,

Ryu³

2016

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

Section: Design Considerationsmentioning

confidence: 99%

A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique

Rastegar¹,

Lim²,

Ryu³

2016

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…제안된 회로는 그림 1에서와 같이 입력 단에는 캐패시터 크로스 커플링 방법을 사용하 여 저전력 입력 정합을 구현하였고, 추가적인 전력 소모없이 이득을 증가시키기 위해 전류 재사용 방식 을 사용하였다 [2], [3] . 전류 재사용단의 공진을 위한 인 덕터의 크기를 줄이기 위하여 병렬 LC 회로를 사용 하였다 [4] . 있다 [1], [5] .…”

Section: ⅱ 저전력 저잡음 증폭기 설계unclassified

“…또한 전류 재사용 방법을 사용하여 하나의 전류원으로 두 개의 증폭기를 작동시켜 회로 전체의 전력 소모를 최소화 하였다 [2], [3] . 전류 재사용단에 사용된 인덕터의 크기 를 줄이기 위하여 캐패시터를 병렬로 연결하여 실효 인덕턴스를 증가시킴으로써 작은 크기의 인덕터를 사용해 공진을 할 수 있었다 [4] .…”

unclassified

Design of a Low Power Capacitor Cross-Coupled Common-Gate Low Noise Amplifier

Shim¹,

Jeong²

2012

The Journal of Korean Institute of Electromagnetic Engineering

View full text Add to dashboard Cite

This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 μm CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled gm-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

show abstract

“…This paper discusses one ultra-wideband LNA design based on current-reused topology and stagger tuning technique [5,7,12,14]. By proper optimization, the LNA achieves a −3 dB bandwidth from 48 to 62 GHz.…”

Section: Introductionmentioning

confidence: 99%

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

Feng

et al. 2015

Circuits Syst Signal Process

View full text Add to dashboard Cite

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a currentreused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the currentreused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum S 21 gain of 11.4 dB gain with a −3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the Circuits Syst Signal Process measured S 11 and S 12 are less than −10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.

show abstract

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

Cited by 21 publications

References 8 publications

A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique

A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique

Design of a Low Power Capacitor Cross-Coupled Common-Gate Low Noise Amplifier

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

Contact Info

Product

Resources

About