Low phase noise Ku-band PLL-IC with &amp;#x2212;104.5dBc/Hz at 10kHz offset using SiGe HBT ECL PFD

Tsutsumi, Koji; Komaki, Masahiko; Shimozawa, Mitsuhiro; Suematsu, Noriharu

doi:10.1109/apmc.2009.5384526

Cited by 5 publications

(7 citation statements)

References 7 publications

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“…A conventional PLL designed in a CMOS or BiCMOS technology is usually implemented using a phase frequency [12][13][14][15]. The PFD can be implemented using two D-type flip flops and an AND gate [13].…”

Section: Phase Detector and Phase Control Designmentioning

confidence: 99%

“…at 28 GHz, the Q-value of the custom made MOM capacitors exceeds that of the MIM capacitors provided by the SiGe technology [8]. Since the supply is 1.5 V and the process does not have any MOS devices it is difficult to design the logic blocks required for a conventional phase frequency detector using a charge pump [9,[12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 98%

“…The phase detector (PD) [12][13][14][15][16] is using a Gilbert type architecture [17][18][19]. The loop filter is implemented as an active filter followed by a passive RC link [17].…”

Section: Introductionmentioning

confidence: 99%

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A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit

Tired

Sjöland

Sandrup

et al. 2015

Analog Integr Circ Sig Process

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This paper presents two circuits, a complete 1.5 V 28 GHz SiGe beam steering PLL and a standalone 28 GHz QVCO with I/Q phase imbalance detection and compensation. The circuits were designed in a SiGe process with f T = 200 GHz. The PLL is intended to be used for beam steering in an 81-86 GHz E-band transmitter. Phase control is implemented by DC current injection at the output of a Gilbert architecture phase detector showing a simulated phase control sensitivity of 1.2°/lA over a range close to 180°. The simulations use layout parasitics for the QVCO, frequency divider, and phase detector, and an electromagnetic model for the QVCO inductors. The divider is implemented with four cascaded divide-by-two current-mode-logic blocks for a reference frequency of 1.75 GHz. For closed loop simulations of PLL noise and stability, the QVCO is represented with a behavior model with added phase noise. This simulation technique enabled faster simulation time of the PLL. The PLL in band phase noise at 1 MHz offset equals -115 dBc/Hz. Excluding output buffers, the entire PLL consumes 52 mW plus a minimum 7 mW from a variable high voltage supply required to extend the PLL locking range. The measured phase noise of the standalone QVCO equals -100 dBc/Hz at 1 MHz offset. Since E-band radio links utilize higher order QAM modulation, the bit-error rate is sensitive to I/Q phase error. In the measured standalone QVCO with I/Q phase imbalance detection and compensation, the error is detected in two cross coupled active mixers that have an output DC level proportional to the phase error. The error can then be eliminated adjusting the bias of four varactors connected to the QVCO outputs. The current consumption of the chip equals 14 mA from a 1.5 V supply and 57 mA from a 2.5 V supply dedicated to the detector and 28 GHz output measurement buffers.

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Section: Phase Detector and Phase Control Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

See 1 more Smart Citation

A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit

Tired

Sjöland

Sandrup

et al. 2015

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…The in-band multiplication of a PFD's phase noise can create difficulties in RF synthesizer design [1]- [3]. Consider, as an example, a 5-GHz synthesizer targeting IEEE802.11a applications.…”

Section: A Motivationmentioning

confidence: 99%

Analysis of Phase Noise in Phase/Frequency Detectors

Homayoun

Razavi

2013

IEEE Trans. Circuits Syst. I

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The phase noise of phase/frequency detectors can significantly raise the in-band phase noise of frequency synthesizers, corrupting the modulated signal. This paper analyzes the phase noise mechanisms in CMOS phase/frequency detectors and applies the results to two different topologies. It is shown that an octave increase in the input frequency raises the phase noise by 6 dB if flicker noise is dominant and by 3 dB if white noise is dominant. An optimization methodology is also proposed that lowers the phase noise by 4 to 8 dB for a given power consumption. Simulation and analytical results agree to within 3.1 dB for the two topologies at different frequencies.

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“…The PLDRO is the most widely used for a local oscillator for such high frequency bands due to its superior phase noise characteristics compared with the PLL IC based approach. Millimeter wave SiGe based integer-N PLL IC phase noise performance has recently improved substantially [1][2][3], but fractional PLL with the same technology still shows inadequate performance compared with its integer counterpart, i.e., about 90 dB in-band phase noise and less than 70 dB spurious [4,5]. This paper presents a PLDRO structure that has output frequency that is not an integer multiple of the reference frequency, and verifies the structure by analyses and experiments.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a Pldro With a Fractional Multiple Frequency of Reference

Chang¹,

Park²

2014

PIER Letters

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Abstract-A PLDRO (Phase Locked Dielectric Resonator Oscillator) with the output frequency of a fractional multiple of reference is proposed and implemented. The key element in the proposed PLDRO is an image rejection mixer placed between a VCDRO (Voltage Controlled Dielectric Resonator Oscillator) and SPD (Sampling Phase Detector). The image rejection mixer shifts the coupled signal from the VCDRO before the signal feeds the SPD. Therefore, the output frequency of the PLDRO can be realized such that it is not harmonically related with its reference frequency. The frequency divider and multiplier generate the IF frequency for the mixer from the reference frequency. The general PLL (Phase Locked Loop) design parameters such as the damping coefficient and the natural frequency are derived for the proposed topology of the PLDRO. A 7.25 GHz PLDRO with a 100 MHz reference, intended for use as a local oscillator for a ka band Block-up Converter (BUC), is designed and measured. A BJT (Bipolar Junction Transistor) is used as an active component of the VCDRO and a modified two micro-strip line coupled DR model is presented and used for frequency tuning range estimation. The measured phase noise at 10 kHz/100 kHz offset is 101 dBc/Hz and 115 dBc/Hz, respectively. The fabricated PLDRO size is 100 mm by 105 mm by 23 mm including a 100 MHz reference crystal oscillator.

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Low phase noise Ku-band PLL-IC with −104.5dBc/Hz at 10kHz offset using SiGe HBT ECL PFD

Cited by 5 publications

References 7 publications

A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit

A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit

Analysis of Phase Noise in Phase/Frequency Detectors

Implementation of a Pldro With a Fractional Multiple Frequency of Reference

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