Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor

Pham, Hung-Manh; Pillement, Sébastien; Piestrak, Stanisław J.

doi:10.1109/tc.2012.55

Cited by 52 publications

(28 citation statements)

References 13 publications

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“…The Lockstep scheme based on DWC, detects the presence of fault in the system [1]. Figure 2 shows the lockstep scheme.…”

Section: A Fault Detectionmentioning

confidence: 99%

“…A Fault tolerant configuration engine which is made fault tolerant using TMR technique locates the position of single bit error in the faulty core and recovers the core from fault [1] .The configuration engine consists of a CRC generator, CRC checker and a PicoBlaze core. Figure 4 shows the Configuration engine based on TMR technique.…”

Section: B Fault Correctionmentioning

confidence: 99%

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Design of Soft error tolerance technique for FPGA based soft core processors

Safarulla¹,

Manilal²

2014

2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies

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SRAM-based FPGAs are susceptible to radiation induced temporary faults called as single-event upsets (SEUs) or Soft errors. Soft errors affects or changes only some logic states of memory elements, but the device itself is not permanently damaged. SEUs may directly alter the logic states of any static memory element or induce changes to configuration memory. A new fault detection system architecture can be incorporated on any SRAM based FPGA with integrated soft core processors. It allows for detection of error in the system and also detects the processor with the error, so that the system can continue execution with the fault free processor. The fault detection system consists of a Lockstep scheme which is based on DWC technique. Lockstep Scheme detects the presence of error in the system but fails to point in which core, error is present. The Faulty core is detected using RESO Method which is based on DWC-CED technique. Once the faulty core is detected, fault tolerance is achieved using Fault tolerant Configuration Engine and by Hamming method. Fault Tolerant Configuration engine built on the basis of the PicoBlaze core, detects the fault location using CRC method and eliminates the error by frame based reconfiguration and is made fault-tolerant using triple modular redundancy (TMR). SEC using hamming method detects and corrects single bit error. Both the cores are synchronized back after fault recovery using CRB. The coding is done in VHDL language, synthesized using Xilinx ISE 13.2 and simulated using ISim.

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“…The Lockstep scheme based on DWC, detects the presence of fault in the system [1]. Figure 2 shows the lockstep scheme.…”

Section: A Fault Detectionmentioning

confidence: 99%

Section: B Fault Correctionmentioning

confidence: 99%

Design of Soft error tolerance technique for FPGA based soft core processors

Safarulla¹,

Manilal²

2014

2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies

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“…Among hardware redundancy techniques, the most popular is the NMR (N-Modular Redundancy) which consists in replicating the hardware responsible for processing information in n modules. The modules are executed simultaneously and the processing result is determined by a voting system .The output result is equal to the most common value among the modules or the calculated mean value [5,12]. Normally this technique is used in two variants: TMR (Triple Modular Redundancy) and DWC (Duplication with Comparison).…”

Section: A Techniques Using Hardware Redundancymentioning

confidence: 99%

“…Normally this technique is used in two variants: TMR (Triple Modular Redundancy) and DWC (Duplication with Comparison). The latter only avoids the error to be propagated, since in case of failure, the application takes an action to cancel the error propagation [12]. Figure 1 shows the implementation of NMR model and Figure 2 shows the DWC model.…”

Section: A Techniques Using Hardware Redundancymentioning

confidence: 99%

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Development of a Fault Injection System to Test a Weather Station Based on Rapid Prototyping Platform

Kruger¹,

Iaione²

2013

2013 IEEE 10th International Conference on High Performance Computing and Communications &Amp; 2013 IEEE International Conferen

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Fault injection has been an important mechanism to test the dependability properties of a system. Through this mechanism, it is possible to analyze the behavior of a computer program in case of anomalies and to obtain useful statistics to measure the effectiveness of techniques for fault tolerance. In areas such as telecommunications, aviation and finance, the use of fault tolerance is a common practice, although, in the development of simple embedded systems it usually does not occur. Due to this reason, there is a need to create tools for noninvasive tests that allow simulating faults without dramatically increasing the system complexity. This article presents some of the techniques often used to impose fault tolerance and describes a system developed for fault injection, which operates by inserting faults in certain memory regions to change the data and to cause crashes in a rapid prototyping platform for microcontrollers. At the end of this article the results are presented.

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