Low overhead delay testing of ASICs

At-Speed Structural Test For High-Performance ASICs

“…Transition fault test application is being widely carried out in industry [1,8,10,12,19]. In [1], methods for at-speed built-in self test (BIST) and deterministic test are presented.…”

“…Moreover, only 5 functional clock pulses can be applied. In [8], the authors describe a method to perform delay test for general level-sensitive scan (LSSD) ASIC designs. Figure 1(a) illustrates an LSSD latchpair; the A and B clocks are used for scan shift and the C clock is the system capture clock.…”

“…The parent mode is used to scan in the values for the PLL frequency control latches and to set up the ASST control logic for correct operation. A small number of high-speed scan chain delay test patterns are also applied in the parent mode using the method presented in [8] to detect delay defects in scan chains that are not designed to be tested at functional speed. Once the control values have been scanned in to latches in the parent mode, the CUT enters the child mode, in which the PLL frequency control latches and other control logic is bypassed and not allowed to capture (illustrated later in Figure 6).…”

“…This ensures that the PLLs are not disturbed and can continue to pulse while each ASST test pattern is scanned into the logic and applied at-speed. At the end of test application in the child mode, the CUT can be once again put into the parent mode for clean-up transition test patterns to be applied using tester clocks as in [8].…”

“…Delay faults in logic across clock domains are not tested atspeed because the domains are driven by asynchronous PLLs. These faults are tested using the methods in [8].…”