Low-overhead Aging-aware Resource Management on Embedded GPUs

Lee, Haeseung; Shafique, Muhammad; Faruque, Mohammad Abdullah Al

doi:10.1145/3061639.3062277

Cited by 11 publications

(3 citation statements)

References 21 publications

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“…Those kernels with a high slice utilization have very limited power-off opportunities and aging mitigation as discussed in Sections 5.3 and 6. At a higher granularity level, there are some proposals that dynamically power off whole compute units [12], [21]. In contrast, our fine-grain proposals only depend on register compression capabilities, which allow powering off registers in spite of being actually used by the kernel.…”

Section: Related Workmentioning

confidence: 99%

“…For instance, for a 45nm technology node, NBTI can cause a 25% performance degradation after 3 years [12]. Moreover, as technology scales down and aging intensifies, NBTI is becoming the principal source of transistor degradation [21], [36], compromising not only performance, but power consumption and area due to enlarged cell designs and transistor design margins required to compensate the NBTI effect [10].…”

Section: Introductionmentioning

confidence: 99%

“…Fortunately, when turned off, transistors not only stop degrading, but they partially recover from the NBTI effect [19]. Therefore, some works have attacked NBTI in GPUs by switching off those memory structures that are not used by GPU applications (kernels) [27], [12] or have severely aged [21]. Other works propose kernel compilation techniques based on aging information [24].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Aging-Aware GPU Register File Design Based on Data Redundancy

Valero

Candel

Gracia

et al. 2019

IEEE Trans. Comput.

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Nowadays, GPUs sit at the forefront of high-performance computing thanks to their massive computational capabilities. Internally, thousands of functional units, architected to be fed by large register files, fuel such a performance. At deep nanometer technologies, the SRAM memory cells that implement GPU register files are very sensitive to the Negative Bias Temperature Instability (NBTI) effect. NBTI ages cell transistors by degrading their threshold voltage V th over the lifetime of the GPU. This degradation, which manifests when a cell keeps the same logic value for a relatively long period of time, compromises the cell read stability and increases the transistor switching delay, which can lead to wrong read values and eventually exceed the processor cycle time, respectively, so resulting in faulty operation. This work proposes architectural mechanisms leveraging the redundancy of the data stored in GPU register files to attack NBTI aging. The proposed mechanisms are based on data compression, power gating, and register address rotation techniques. All these mechanisms working together balance the distribution of logic values stored in the cells along the execution time, reducing both the overall V th degradation and the increase in the transistor switching delays. Experimental results show that a conventional GPU register file suffers the worst case for NBTI, since a significant fraction of the cells maintain the same logic value during the entire application execution (i.e., a 100% '0' and '1' duty cycle distributions). On average, the proposal reduces these distributions by 58% and 68%, respectively, which translates into V th degradation savings by 54% and 62%, respectively.

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Section: Related Workmentioning

confidence: 99%