An Aging-Aware GPU Register File Design Based on Data Redundancy

Abstract

Nowadays, GPUs sit at the forefront of high-performance computing thanks to their massive computational capabilities. Internally, thousands of functional units, architected to be fed by large register files, fuel such a performance. At deep nanometer technologies, the SRAM memory cells that implement GPU register files are very sensitive to the Negative Bias Temperature Instability (NBTI) effect. NBTI ages cell transistors by degrading their threshold voltage V th over the lifetime of the GPU. This degradation, which manifests when a cell keeps the same logic value for a relatively long period of time, compromises the cell read stability and increases the transistor switching delay, which can lead to wrong read values and eventually exceed the processor cycle time, respectively, so resulting in faulty operation. This work proposes architectural mechanisms leveraging the redundancy of the data stored in GPU register files to attack NBTI aging. The proposed mechanisms are based on data compression, power gating, and register address rotation techniques. All these mechanisms working together balance the distribution of logic values stored in the cells along the execution time, reducing both the overall V th degradation and the increase in the transistor switching delays. Experimental results show that a conventional GPU register file suffers the worst case for NBTI, since a significant fraction of the cells maintain the same logic value during the entire application execution (i.e., a 100% '0' and '1' duty cycle distributions). On average, the proposal reduces these distributions by 58% and 68%, respectively, which translates into V th degradation savings by 54% and 62%, respectively.

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

“…Depending on the benchmark, these percentages range from 54 (QRandS) to 93% (SConv), with an average of 74%. This percentage is higher than those from previous work reporting the average register file utilization [1], [44].…”

“…This paper leverages the data compression mechanism proposed in [44], where three different regular data patterns are identified, namely constant, single-∆, and double-∆ patterns.…”

“…Power gating helps not only to reduce static energy consumption but also to mitigate aging effects, particularly the Negative Bias Temperature Instability (NBTI) phenomenon [12]. Unlike Warped-Compression and EREER, RC+RAR is a technique that switches off entire registers by storing the compressed data in an auxiliary NBTI-free memory array [44]. Combining power gating with a register address rotation approach, all the register file cells can be powered off and age uniformly over time.…”

“…Recent work focusing on GPU register files leverage data compression to save energy [27], [48], [50], to mitigate transistor aging phenomena [44], or to deal with transient faults [32].…”

RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU

“…Algunos trabajos recientes explotan la compresión de datos en el banco de registros de la GPU para reducir energía [14], [31], [32], mitigar efectos de envejecimiento de los transistores [28] o para lidiar con fallos transitorios [18]. Sin embargo, a nuestro mejor entender, la compresión no se ha utilizado con anterioridad para eludir fallos permanentes en bancos de registros GPU.…”