Low On-State Voltage and EMI Noise 4H-SiC IGBT With Self-Biased Split-Gate pMOS

Wu, Lijuan; Liu, Mengjiao; Zhang, Mengyuan; Ji, Liang; Ye, Gang; Zhang, Tengfei; Liu, Qing

doi:10.1109/ted.2022.3231808

Cited by 1 publication

(1 citation statement)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finally, when the concentration of the LBD is 5 × 10 15 cm −3 , the breakdown voltage of the DT-LBDMOS can reach about 1400 V and the threshold voltage of the DT-LBDMOS is about 3.3 V. We made use of TCAD simulations to simulate the device's electrical properties of the proposed and conventional structures. We considered some of the key models during the simulation, such as mobility saturation in the large electric field, SRH and Auger recombination, Okuto-Crowell impact ionization, bandgap narrowing, incomplete ionization, IALMob mobility degradation [22], and some temperature-dependent models and thermal boundary conditions were considered, including the thermodynamic model and the Ana-lyticTEP thermoelectric power model [23]. In order to make the simulation results more realistic, the traps and fixed charges at SiC/SiO 2 interface were also considered [23].…”

Section: Device Structure and Mechanismmentioning

confidence: 99%

A Low-Loss 1.2 kV SiC MOSFET with Improved UIS Performance

Zhang

et al. 2023

Micromachines

Self Cite

View full text Add to dashboard Cite

In this article, a 1.2-kV-rated double-trench 4H-SiC MOSFET with an integrated low-barrier diode (DT-LBDMOS) is proposed which eliminates the bipolar degradation of the body diode and reduces switching loss while increasing avalanche stability. A numerical simulation verifies that a lower barrier for electrons appears because of the LBD; thus, a path that makes it easier for electrons to transfer from the N+ source to the drift region is provided, finally eliminating the bipolar degradation of the body diode. At the same time, the LBD integrated in the P-well region weakens the scattering effect of interface states on electrons. Compared with the gate p-shield trench 4H-SiC MOSFET (GPMOS), the reverse on-voltage (VF) is reduced from 2.46 V to 1.54 V; the reverse recovery charge (Qrr) and the gate-to-drain capacitance (Cgd) are 28% and 76% lower than those of the GPMOS, respectively. The turn-on and turn-off losses of the DT-LBDMOS are reduced by 52% and 35%. The specific on-resistance (RON,sp) of the DT-LBDMOS is reduced by 34% due to the weaker scattering effect of interface states on electrons. The HF-FOM (HF-FOM = RON,sp × Cgd) and the P-FOM (P-FOM = BV2/RON,sp) of the DT-LBDMOS are both improved. Using the unclamped inductive switching (UIS) test, we evaluate the avalanche energy of devices and the avalanche stability. The improved performances suggest that DT-LBDMOS can be harnessed in practical applications.

show abstract

Section: Device Structure and Mechanismmentioning

confidence: 99%