Low-Loss Polysilicon Waveguides Suitable for Integration within a High-Volume Electronics Process

Orcutt, Jason S.; Tang, Sanh; Kramer, S.; Li, Hanqing; Stojanović, Vladimir; Ram, Rajeev J.

doi:10.1364/cleo_si.2011.cthhh2

Cited by 4 publications

(8 citation statements)

References 3 publications

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“…A basic set of the required photonic devices that must be integrated in the process is shown in Figure 7. Currently, device and process development has focused on either solid phase epitaxy (SPE) silicon waveguides [34,35] or deposited polycrystalline silicon waveguides [3]. Both approaches have yielded waveguide losses below 10 dB/cm.…”

Section: Drammentioning

confidence: 99%

Integration of silicon photonics into electronic processes

2013

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Front-end monolithic integration has enabled photonic devices to be fabricated in bulk and thin-SOI CMOS as well as DRAM electronics processes. Utilizing the CMOS generic process model, integration was accomplished on multi-project wafers that were shared by standard electronic customers without requiring in-foundry process changes. Simple die or wafer-level post-processing has enabled low-loss waveguides by the removal of the substrate within photonic regions. The custom-process model of the DRAM industry instead enabled optimization of the photonic device fabrication process and the potential elimination of post-processing requirements. Integrated singlecrystalline silicon waveguide loss of ~3 dB/cm has been achieved within a 45nm thin-SOI CMOS process that is currently used to manufacture microprocessors [1]. A fully monolithic photonic transmitter including a pseudo-random bit sequence (PRBS) generating digital backend was also demonstrated within this process [1]. The constraints of zero-change integration have limited achieved polysilicon waveguide loss to ~50 dB/cm with commercially available bulk CMOS processes [2]. Custom polysilicon deposition and processing conditions available for DRAM integration have also led to the demonstration of ~6 dB/cm loss waveguides suitable for integration within electronics processes utilizing bulk silicon starting substrates [3]. An overview of required process features, device design guidelines and integration methodology tradeoffs will be presented. Relevant device metrics of area and energy efficiency as well as achievable photonic device performance will be presented within the context of monolithic front-end integration within state-ofthe-art electronics processes. Applications of this research towards the implementation of a computer system utilizing photonic interconnect for core-to-memory communication will also be discussed.

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Section: Drammentioning

confidence: 99%

Integration of silicon photonics into electronic processes

2013

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“…This constraint forbids the integration of standard single-crystalline silicon waveguides that have been previously demonstrated to provide low loss. Instead, deposited silicon waveguides suitable for integration within DRAM memory processes to enable photonic interconnect from processors to memory within future computation systems are being actively developed [10,11]. Polycrystalline silicon waveguides are desirable in this role as propagation losses below 10 dB/cm are achievable [12,13] using materials already common in such processes.…”

Section: Dram Integrationmentioning

confidence: 99%

“…Further, the low-loss performance was not verified to withstand the high-temperature steps present in electronics processes. To address this need we developed thin poly-Si waveguides fabricated in a complete 300 mm wafer process representative of state-of-the-art memory processes with end-of-line waveguide losses below 10 dB/cm for the first time [10]. The waveguide core was first deposited at low-temperature by LPCVD to form an amorphous film.…”

Section: Dram Integrationmentioning

confidence: 99%

“…The cost and barrier-to-entry of drastically modifying these processes in a similar manner is too large to be practical for most applications. Instead, we have demonstrated design and data preparation techniques [6][7][8], post-fabrication processing steps [7][8][9] and infoundry process optimizations [10] that enables photonic integration efforts to leverage the existing infrastructure.…”

Section: Introductionmentioning

confidence: 99%

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Photonic Integration in State-of-the-Art Silicon Electronics Processes

Orcutt

2012

Advanced Photonics Congress

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“…We use our experiences with a 65-nm test chip [21], our feasibility studies for a prototype 32-nm process, predictive electrical device models [22], and interconnect projections [23] to estimate both electrical and photonic device parameters for a target 22-nm technology node. Device-level details about the MIT nanophotonic technology assumed in the rest of this paper can be found in [21], and [24]- [27], although the technology is rapidly evolving such that more recent device-level work uses more advanced device and circuit techniques [28]- [30]. Details about the specific technology assumptions for each case study can be found in our previous system-level publications [3], [12], [13], [15].…”

mentioning

confidence: 99%

Designing Chip-Level Nanophotonic Interconnection Networks

Batten

Joshi

Stojanović

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-Technology scaling will soon enable high-performance processors with hundreds of cores integrated onto a single die, but the success of such systems could be limited by the corresponding chip-level interconnection networks. There have been many recent proposals for nanophotonic interconnection networks that attempt to provide improved performance and energy-efficiency compared to electrical networks. This paper discusses the approach we have used when designing such networks, and provides a foundation for designing new networks. We begin by briefly reviewing the basic silicon-photonic device technology before outlining design issues and surveying previous nanophotonic network proposals at the architectural level, the microarchitectural level, and the physical level. In designing our own networks, we use an iterative process that moves between these three levels of design to meet application requirements given our technology constraints. We use our ongoing work on leveraging nanophotonics in an on-chip title-to-tile network, processor-to-main-memory network, and dynamic random-access memory (DRAM) channel to illustrate this design process.

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Low-Loss Polysilicon Waveguides Suitable for Integration within a High-Volume Electronics Process

Cited by 4 publications

References 3 publications

Integration of silicon photonics into electronic processes

Integration of silicon photonics into electronic processes

Photonic Integration in State-of-the-Art Silicon Electronics Processes

Designing Chip-Level Nanophotonic Interconnection Networks

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