Low Latency Path Prediction Mechanism in 2D-NoC

Rezaei-Ravari, Maryam; Sattari-Naeini, Vahid

doi:10.1109/icee.2018.8472445

Cited by 2 publications

(3 citation statements)

References 22 publications

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“…An Evolving Fuzzy Neural Network (EFuNN) based low latency path prediction algorithm is proposed in [30] to minimize latency issues caused by congestion-aware routing algorithms. The proposed work showed slight improvement in routing latency by incorporating existing congestion information however, the model failed to predict on path congestion.…”

Section: B Related Workmentioning

confidence: 99%

Predicting Networks-on-Chip traffic congestion with Spiking Neural Networks

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Harkin

McDaid

et al. 2021

Journal of Parallel and Distributed Computing

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Section: B Related Workmentioning

confidence: 99%

Predicting Networks-on-Chip traffic congestion with Spiking Neural Networks

Javed

Harkin

McDaid

et al. 2021

Journal of Parallel and Distributed Computing

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“…Artificial Neural Networking (ANN) model use buffer occupancy level to predict location of potential hotspot router with 65-92% accuracy on synthetic and real-time dataset [15]. An Evolving Fuzzy Neural Network (EFuNN), which is inspired by the combination of NNs and the fuzzy logic is proposed to predict congestion-free minimal path to improve network latency [2].…”

Section: Background and Related Workmentioning

confidence: 99%

“…Different on-chip interconnect solutions were proposed to optimize usage of shared network paths. Networks-on-Chip (NoC) is proposed as a scalable and modular communication architecture to provide multiple paths between cores and hence reduce network latency issues [2]. Depending on the application mapping and routing algorithm NoCs can support thousands of cores where it is facilitating huge communication workloads, that can ultimately cause congestion problems [3].…”

Section: Introductionmentioning

confidence: 99%

Exploring Spiking Neural Networks for Prediction of Traffic Congestion in Networks-on-Chip

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Harkin

McDaid

et al. 2020

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

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Networks-on-Chip (NoC) is the most modular and scalable solution for next generation hardware communication where significant data traffic loads are shared across many communication paths. One key challenge in maximising NoC performance is traffic congestion. The management of congestion at the earliest stage can significantly minimize the impact on NoC throughput. Prediction of NoC congestion offers a pre-emptive strategy in maximising NoC throughput. This paper proposes a novel spiking neural network (SNN) approach to prediction of traffic congestion. The proposed SNN exploits the temporal nature of the traffic to identify congestion patterns. The proposed SNN explores two models and both are trained and evaluated to predict local congestion 30 clock cycles in advance of occurring. Results shows that the SNN predictor utilizes 9 times less hardware area than previous approaches and can achieved up to 96.59% in accuracy.

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Low Latency Path Prediction Mechanism in 2D-NoC

Cited by 2 publications

References 22 publications

Predicting Networks-on-Chip traffic congestion with Spiking Neural Networks

Predicting Networks-on-Chip traffic congestion with Spiking Neural Networks

Exploring Spiking Neural Networks for Prediction of Traffic Congestion in Networks-on-Chip

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