Exploring Spiking Neural Networks for Prediction of Traffic Congestion in Networks-on-Chip

Javed, Aqib; Harkin, Jim; McDaid, Liam; Liu, Junxiu

doi:10.1109/iscas45731.2020.9180630

Cited by 13 publications

(10 citation statements)

References 23 publications

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“…This exploration is done in conjunction with topology design, investigating hybrid and hierarchical topologies such as combining ring, mesh and star, to name a few ( Carrillo et al , 2013 ; Subbulakshmi and Balamurugan, 2014 ). In addition, some general NoC-based system designs have explored the actual compression of data packets ( Carrillo et al , 2012 ; Maruyama et al , 2017 ) and prediction of data traffic ( Das and Ghosal, 2018 ; Javed et al , 2020 ; Maruyama et al , 2017 ) as a means to accelerate the execution of the application. These design decisions establish the challenge, complexity and motivation, to investigate NoC traffic compression and prediction techniques as mechanisms to advance SRA performances further.…”

Section: Discussionmentioning

confidence: 99%

Hardware acceleration of genomics data analysis: challenges and opportunities

2021

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The significant decline in the cost of genome sequencing has dramatically changed the typical bioinformatics pipeline for analysing sequencing data. Where traditionally, the computational challenge of sequencing is now secondary to genomic data analysis. Short read alignment (SRA) is a ubiquitous process within every modern bioinformatics pipeline in the field of genomics and is often regarded as the principal computational bottleneck. Many hardware and software approaches have been provided to solve the challenge of acceleration. However, previous attempts to increase throughput using many-core processing strategies have enjoyed limited success, mainly due to a dependence on global memory for each computational block. The limited scalability and high energy costs of many-core SRA implementations pose a significant constraint in maintaining acceleration. The Networks-On-Chip (NoC) hardware interconnect mechanism has advanced the scalability of many-core computing systems and, more recently, has demonstrated potential in SRA implementations by integrating multiple computational blocks such as pre-alignment filtering and sequence alignment efficiently, while minimising memory latency and global memory access. This paper provides a state of the art review on current hardware acceleration strategies for genomic data analysis, and it establishes the challenges and opportunities of utilising NoCs as a critical building block in next-generation sequencing (NGS) technologies for advancing the speed of analysis.

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Section: Discussionmentioning

confidence: 99%

Hardware acceleration of genomics data analysis: challenges and opportunities

2021

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“…Javed et al [24] presented a unique spiking neural network (SNN) technique to traffic congestion prediction. To identify congestion patterns, the suggested SNN takes use of the temporal character of traffic.…”

Section: Literature Surveymentioning

confidence: 99%

“…Similarly, in [21,23] the coding scheme was ineffective because of its error-correcting capabilities and presence of crosstalk. [24] requires high device performance and [25] is not focusing on runtime fault. [26] takes more time during computation and [27] need to consider network component failures.…”

Section: Literature Surveymentioning

confidence: 99%

Prediction of Intermittent Failure by Presage Debacle Model in Network on Chip

Singh¹,

Ravindra²,

Naik³

2022

IJCNIS

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With the emergence of deep sub-micron technology, the reliability issues in on-chip interconnect has enormously increased. This includes single event upsets, like soft errors, and hard faults which are rapidly becoming important factors to be considered. Aggressive technology scaling renders these architectures vulnerable to system performance, intermittent failure, capacitive crosstalk, and power dissipation problem. To improve the performance of the area and power consumption along with bandwidth, throughput and latency, a Buffer Potency Power Gating Technique is carried out to predict the Intermittent Failure by Presage Debacle Model in Network on Chip. In the Presage Debacle Model, the links present in the application-specific topology are provided with real application traffic to assist in prediction of the intermittent failure. By predicting the failure, the output of the model provides the power dissipated over the connection of the application link. Then the crosstalk noise in the topology is reduced by the Adaption of Simulated Annealing (SA) based Particle Swarm Optimization (PSO) congruence algorithm. The optimization congruence algorithm assigns each task in the application software to each node in the topology to determine the network's optimal output. It continuously changes the task park position in the topology system and reduces the crosstalk of the NoC. Consecutively, the area and power consumption are minimized by Buffer Potency Power Gating Technique. Buffer efficiency is increased and the power-gating is a practical way to mitigate NoC power control schemes properly and effectively without any loss in performance. Thus the prediction of intermittent failure is obtained by utilizing NoC to improve the performance of area and power consumption.

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“…e term neuromorphic computing is a concept developed by Carver Mead in the late 1980s describing the use of very-large-scale integration (VLSI) systems containing electronic analog circuits to mimic the neural and biological architecture present in the nervous system. Currently, the term neuromorphic is used to describe analog systems, digital systems, analog/digital complex systems, and software that model neural systems [1][2][3]. Interprocessor communication is supported on an effective multicast foundation managed by neurobiology.…”

Section: Introductionmentioning

confidence: 99%

Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC‐Based Neuromorphic Systems

Trik

Mozaffari

Bidgoli

2021

Computational Intelligence and Neuroscience

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Effective and efficient routing is one of the most important parts of routing in NoC-based neuromorphic systems. In fact, this communication structure connects different units through the packets routed by routers and switches embedded in the network on a chip. With the help of this capability, not only high scalability and high development can be created, but by decreasing the global wiring to the chip level, power consumption can be reduced. In this paper, an adaptive routing algorithm for NoC-based neuromorphic systems is proposed along with a hybrid selection strategy. Accordingly, a traffic analyzer is first used to determine the type of local or nonlocal traffic depending on the number of hops. Then, considering the type of traffic, the RCA and NoP selection strategies are used for the nonlocal and local strategies, respectively. Finally, using the experiments that performed in the simulator environment, it has been shown that this solution can well reduce the average delay time and power consumption.

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Exploring Spiking Neural Networks for Prediction of Traffic Congestion in Networks-on-Chip

Cited by 13 publications

References 23 publications

Hardware acceleration of genomics data analysis: challenges and opportunities

Hardware acceleration of genomics data analysis: challenges and opportunities

Prediction of Intermittent Failure by Presage Debacle Model in Network on Chip

Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC‐Based Neuromorphic Systems

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