Low-Latency Pairing Processor Architecture Using Fully-Unrolled Quotient Pipelining Montgomery Multiplier

Sakamoto, Junichi; Nagahama, Yusuke; Fujimoto, Daisuke; Okuaki, Yota; Matsumoto, Tsutomu

doi:10.1109/asianhost47458.2019.9006671

Cited by 2 publications

(6 citation statements)

References 10 publications

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“…Existing pairing processors on FPGAs [8], [9], [10], [11], [14], [15] run at 200-300 MHz, which is lower than the maximum operating frequency of the FPGAs, 600-800 MHz. This is mainly because the existing studies focus on low-latency computation.…”

Section: B Low Operating Frequencymentioning

confidence: 99%

“…Sakamoto et al [15] proposed a pairing processor based on Yao et al's work [8], and their pairing processors have similar architectures. While Sakamoto et al aimed to develop a low-latency and large-scale pairing processor with fully unrolled quotient pipelining Montgomery multiplication (QPMM), Yao et al aimed to achieve a good area-speed efficiency with the residue number system (RNS).…”

Section: Related Studiesmentioning

confidence: 99%

“…Architecture Overview Fig. 3 shows the overall architecture of our pairing processor, which is an improved version of the one from our previous study [15]. This architecture is mainly designed to accelerate the F p 2 arithmetic frequently appearing in the pairing computation.…”

Section: Proposed Pairing Processor Architecturementioning

confidence: 99%

“…The sequencer issues control signals to control the operation of each module. The sequencer has a built-in ROM with 2048 entries, which contains a pairing computation program optimized for the 18-stage pipeline architecture [15]. Because the pipeline of our architecture has more than 18 stages (89 stages for BN254 pairing and 121 stages for BLS12_381 pairing), this program cannot run efficiently.…”

Section: B Operation Modules 1) Sequencermentioning

confidence: 99%

“…Our program works under the condition that σ < 18τ ; therefore, we set τ = 5 for the BN254 pairing and τ = 7 for the BLS12_381 pairing. Our pairing program is optimized by various techniques described in [3], including twisted elliptic curves, sparse multiplication, and compressed squaring techniques (see [15] for the detailed scheduling).…”

Section: B Operation Modules 1) Sequencermentioning

confidence: 99%

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High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications

Sakamoto,

Fujimoto,

Anzai

et al. 2024

IEEE Trans. VLSI Syst.

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This study focuses on the acceleration of cryptographic pairing operations on field-programmable gate arrays (FPGAs) for server-side applications. Previous studies on FPGA pairing implementations focused on area efficiency for embedded devices, trying to achieve maximum performance with minimal circuit resources. However, their architectures are likely to be inefficient for server-side applications, where the primary interest is maximum performance when FPGA resources are finished. Their architectures are inefficient for two reasons: low utilization of the digital signal processor (DSP) and low operation frequency. In this study, we propose a high-throughput pairing processor architecture for server-side FPGAs, taking full advantage of DSPs. First, we propose a loop-unrolled modular multiplication algorithm that is suitable for a server-side FPGA. The algorithm shows the highest throughput and area efficiency compared to algorithms from previous studies. Second, we design a pairing processor architecture that embeds the proposed modular multiplier, thus, maintaining its high throughput by supporting redundant adders and interleaved executions. We evaluate BN254 and BLS12_381 pairings on the proposed processor architecture and the evaluation results show that it achieves good throughput that is approximately two and five times faster than that from previous studies, respectively.

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Section: B Low Operating Frequencymentioning

confidence: 99%

Section: Related Studiesmentioning

confidence: 99%

Section: Proposed Pairing Processor Architecturementioning

confidence: 99%

Section: B Operation Modules 1) Sequencermentioning

confidence: 99%

Section: B Operation Modules 1) Sequencermentioning

confidence: 99%

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High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications

Sakamoto,

Fujimoto,

Anzai

et al. 2024

IEEE Trans. VLSI Syst.

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Compact and Programmable yet High-Performance SoC Architecture for Cryptographic Pairings

Bahadori

Järvinen

2020

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

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Cryptographic pairings are important primitives for many advanced cryptosystems. Efficient computation of pairings requires the use of several layers of algorithms as well as optimizations in different algorithm and implementation levels. This makes implementing cryptographic pairings a difficult task particularly in hardware. Many existing hardware implementations fix the parameters of the pairing to improve efficiency but this significantly limits the generality and practicality of the solution. In this paper, we present a compact and programmable yet high-performance architecture for programmable system-onchip platforms designed for efficient computation of different cryptographic pairings. We demonstrate with real hardware that this architecture can compute optimal ate pairings on a Barreto-Naehrig curve with 126-bit security in 2.18 ms in a Xilinx Zynq-7020 device and occupies only about 3200 slices, 36 DSPs, and 18 BRAMs. We also show that the architecture can support different types of pairings via microcode updates and can be implemented on other reprogrammable devices with very minor modifications.

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Low-Latency Pairing Processor Architecture Using Fully-Unrolled Quotient Pipelining Montgomery Multiplier

Cited by 2 publications

References 10 publications

High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications

High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications

Compact and Programmable yet High-Performance SoC Architecture for Cryptographic Pairings

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