Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon’s Low-Complexity Chase

García-Herrero, Francisco; Sánchez‐Macian, Alfonso; Maestro, Juan Antonio

doi:10.1109/tcsii.2020.2982496

Cited by 1 publication

(2 citation statements)

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“…Developed a three-stage voltage comparator concentrated on improving comparator sensitivity and total gain in this design. B. Prathibha et al [2] suggested a three-stage CMOS comparator with a high-speed operation to gain a lower static & dynamic power dissipation and a smaller offset voltage. Satyabrata et al [3] compare the traditional comparator to the latched and hysteresisbased comparator.…”

Section: Related Workmentioning

confidence: 99%

“…This advancement not only streamlines the decoding process but also underscores the efficiency of the proposed algorithm in optimizing both computation and resource allocation. [2] The primary strategy revolves around elevating the soft decision Channel Bit Error Rate (CBER) by employing asymmetric Log-Likelihood Ratios (LLRs). This approach harmonizes the distribution of LLRs with that of hard breakdown errors induced by resets.…”

Section: Introductionmentioning

confidence: 99%

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Detection Of Soft Errors in Clock Synthesizers and Latency Reduction Throgh Voltage Scaling Mechanism

2024

VLSI

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This paper presents the design of a comparator with low power, low offset voltage, high resolution, and rapid speed. The designed comparator is built on 45 𝑛𝑛𝑛𝑛 flip CMOS technology and runs 4.2 𝐺𝐺 samples per second at nominal voltage. It is a custom-made comparator for a highly linear 4-bit Flash A/D Converter (ADC). The outlined design can operate on a nominal supply of 1.8 V. The comparator offset voltage was elevated because of this mismatch. To compensate for the offset voltage, we followed a decent approach to design the circuits. Therefore, the offset voltage is reduced to 250𝜇𝜇𝜇𝜇. The designed comparator has a unity gain bandwidth of 4.2 𝐺𝐺𝐺𝐺𝐺𝐺 and a gain of 72𝑑𝑑𝑑𝑑 at nominal PVT, which gives us a considerable measure of authority. The dynamic power consumption of the comparator is 48.7𝜇𝜇𝜇𝜇. The layout of this designed comparator has been implemented, and the area of the comparator is 12.3 𝜇𝜇𝑛𝑛 × 15.75 𝜇𝜇𝑛𝑛. The results of pre-and post-layout simulations in various process, voltage, and temperature corners are shown.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%