Detection Of Soft Errors in Clock Synthesizers and Latency Reduction Throgh Voltage Scaling Mechanism

Abstract

This paper presents the design of a comparator with low power, low offset voltage, high resolution, and rapid speed. The designed comparator is built on 45 𝑛𝑛𝑛𝑛 flip CMOS technology and runs 4.2 𝐺𝐺 samples per second at nominal voltage. It is a custom-made comparator for a highly linear 4-bit Flash A/D Converter (ADC). The outlined design can operate on a nominal supply of 1.8 V. The comparator offset voltage was elevated because of this mismatch. To compensate for the offset voltage, we followed a decent approach to design the circuits. Therefore, the offset voltage is reduced to 250𝜇𝜇𝜇𝜇. The designed comparator has a unity gain bandwidth of 4.2 𝐺𝐺𝐺𝐺𝐺𝐺 and a gain of 72𝑑𝑑𝑑𝑑 at nominal PVT, which gives us a considerable measure of authority. The dynamic power consumption of the comparator is 48.7𝜇𝜇𝜇𝜇. The layout of this designed comparator has been implemented, and the area of the comparator is 12.3 𝜇𝜇𝑛𝑛 × 15.75 𝜇𝜇𝑛𝑛. The results of pre-and post-layout simulations in various process, voltage, and temperature corners are shown.