Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

Fischer, K.; Agostinelli, M.; Allen, C.; Bahr, David F.; Bost, M.; Charvát, P.; Chikarmane, V.; Fu, Qundong; Ganpule, C. S.; Haran, Michael E.; Heckscher, M.; Hiramatsu, Hidenori; Hwang, Eui-Seong; Jain, Pulkit; Jin, Ik Kyeong; Kasim, R.; Kosaraju, Satyanarayana; Lee, K. S.; Liu, H.; McFadden, R.S.; Nigam, Siddhartha; Patel, Rakesh; Pelto, C.; Plekhanov, P. S.; Prince, M.; Puls, Conor; Rajamani, Saravanan; Rao, D. Srinivas; Reese, P.; Rosenbaum, Annette; Sivakumar, S.; Song, Bomi; Uncuer, Muhammet; Williams, Sue; Yang, Meng-Ta; Yashar, P.; Natarajan, S.

doi:10.1109/iitc-mam.2015.7325600

Cited by 51 publications

(19 citation statements)

References 2 publications

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“…Modern processors use aspect ratios between 1.2 and 1.5 on the first four (0-3) metal layers. 31 We show a CVD method that natively generates nanoscale wires with a width to height aspect ratio of ~1, close to the optimal one.…”

mentioning

confidence: 77%

Low Resistivity and High Breakdown Current Density of 10 nm Diameter van der Waals TaSe₃ Nanowires by Chemical Vapor Deposition

et al. 2019

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Micron-scale single-crystal nanowires of metallic TaSe3, a material that forms -Ta-Se3-Ta-Se3-stacks separated from one another by a tubular van der Waals (vdW) gap, have been synthesized using chemical vapor deposition (CVD) on a SiO2/Si substrate, in a process compatible with semiconductor industry requirements. Their electrical resistivity was found unaffected by downscaling from the bulk to as little as 7 nm in width and height, in striking contrast to the resistivity of copper for the same dimensions. While the bulk resistivity of TaSe3 is substantially higher than that of bulk copper, at the nanometer scale the TaSe3 wires become competitive to similar-sized copper ones. Moreover, we find that the vdW TaSe3 nanowires sustain current densities in excess of 10 8 A/cm 2 and feature an electromigration energy barrier twice that of copper. The results highlight the promise of quasi-onedimensional transition metal trichalcogenides for electronic interconnect applications and the potential of van der Waals materials for downscaled electronics.

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confidence: 77%

Low Resistivity and High Breakdown Current Density of 10 nm Diameter van der Waals TaSe₃ Nanowires by Chemical Vapor Deposition

et al. 2019

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“…A high-density SRAM cell (1:1:1, PU:PD:PG) [23] is used, and the cell height and width are estimated as 0.14µm and 0.356µm, respectively. The parasitic capacitance for WL, BL, and all control signals, including SAE, ColSel, Write-CLK, WLEN, and address signals, is set as 0.27 fF/µm based on [27]. The input signals, CLK, WEN, address bits, and input data are applied to SRAM with VDDL level for the dual-rail SRAMs.…”

Section: Circuit-level Simulation Resultsmentioning

confidence: 99%

“…The impact of the level-shifting sense amplifier and powergated cross-coupled inverter based level-shifting write driver used in the proposed ELS dual-rail SRAM on area is evaluated. The evaluation is based on process information introduced in [27].…”

Section: Area Evaluationmentioning

confidence: 99%

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

et al. 2020

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An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dualrail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.

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“…While the copper lines are reduced in each technology node, the thickness of the diffusion barriers are not staggered [23,24,25,26,27]. For example, the Intel 14 nm technology has the minimum metal width of 28 nm, 1.57 times smaller than the Intel 22 nm [28,29]. In turn, these technologies have a TaN/Ta diffusion barrier/liner close to 2-3 nm [29].…”

Section: Comparison With the State-of-the-artmentioning

confidence: 99%

Effect of Lines and Vias Density on the BEOL Temperature Distribution

Nunes

Orio²

2019

JICS

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A method to calculate the temperature distribution on the BEOL structure and its impact on the EM in a design environment has been developed and implemented. The study for a 45 nm technology indicated a large temperature variation from the local to the global interconnects, which should be considered for the EM induced resistance increase of the line, in contrast to the standard analysis through a fixed operation temperature throughout the BEOL. The results show that a significant additional temperature above 50°C exist on the layers M1 to M6 due the power dissipated from transistors. The temperature reduction on the local layer is evaluated increasing the number of vias and enlarging the interconnect lines, both with a direct influence on the BEOL thermal distribution. A reduction of 62.9°C is obtained for M1 layer, considering a fraction volume of 40% for lines and 6% for vias.

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Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

Cited by 51 publications

References 2 publications

Low Resistivity and High Breakdown Current Density of 10 nm Diameter van der Waals TaSe₃ Nanowires by Chemical Vapor Deposition

Low Resistivity and High Breakdown Current Density of 10 nm Diameter van der Waals TaSe₃ Nanowires by Chemical Vapor Deposition

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

Effect of Lines and Vias Density on the BEOL Temperature Distribution

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Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

Cited by 51 publications

References 2 publications

Low Resistivity and High Breakdown Current Density of 10 nm Diameter van der Waals TaSe3 Nanowires by Chemical Vapor Deposition

Low Resistivity and High Breakdown Current Density of 10 nm Diameter van der Waals TaSe3 Nanowires by Chemical Vapor Deposition

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

Effect of Lines and Vias Density on the BEOL Temperature Distribution

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Product

Resources

About

Low Resistivity and High Breakdown Current Density of 10 nm Diameter van der Waals TaSe₃ Nanowires by Chemical Vapor Deposition

Low Resistivity and High Breakdown Current Density of 10 nm Diameter van der Waals TaSe₃ Nanowires by Chemical Vapor Deposition