Low-Frequency Series-Resistance Analytical Modeling of Three-Dimensional Metal–Insulator–Metal Capacitors

Bajolet, A.; Clerc, R.; Pananakakis, G.; Tsamados, Dimitrios; Picollet, E.; Segura, N.; Giraudin, J.-C.; Delpech, P.; Montès, L.; Ghibaudo, G.

doi:10.1109/ted.2007.891851

Cited by 10 publications

(8 citation statements)

References 9 publications

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“…8, ESR decreases roughly inversely proportional to frequency at first, during which it is dominated by R d , until it reaches the minimum resistance of R plate . R plate was found to be around 300 to 700mohm, which is near expectation using equations from [8]. There seems to be an optimal design for capacitor dimensions to minimize R plate , which is still under investigation.…”

Section: Measurement Resultsmentioning

confidence: 55%

A Novel High-Density Capacitor Design and Its Fabrication Technique Based on Selective Etching

Tseng¹,

Xie²,

Ngo³

2012

2012 Solid-State, Actuators, and Microsystems Workshop Technical Digest

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The design, fabrication, and characterization of a novel high-density metal-insulator-metal (MIM) multilayer capacitor is reported. In order to interconnect the multiple electrode layers without using numerous photolithography steps, a unique process was developed based on depositing MIM layers onto a substrate with two pillars, fine polishing to expose the multilayer cross sections, and then selectively etching the metals on each pillar to form the capacitor electrodes. For demonstration purpose, only capacitors with two dielectric layers were fabricated, with measurement results verified by a theoretical model. With a dielectric thickness of 200nm, a capacitance density of 0.54fF/m 2 was achieved, which can be easily increased by decreasing dielectric thickness and increasing the number of MIM layers. The capacitor also exhibits low equivalent series resistance (ESR) of 300-700mohms, and can operate up to 63MHz.

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Section: Measurement Resultsmentioning

confidence: 55%

A Novel High-Density Capacitor Design and Its Fabrication Technique Based on Selective Etching

Tseng¹,

Xie²,

Ngo³

2012

2012 Solid-State, Actuators, and Microsystems Workshop Technical Digest

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“…al's work [17]. This model, originally developed for a 3D MIM structure in the interconnection levels of an LSI die [9], takes into account electrical distribution along the electrodes and is in agreement with both 3D numerical simulations and experiments [17].…”

Section: Copper Partial-filling Impact On Esrmentioning

confidence: 58%

Through Silicon Capacitor co-integrated with TSV as an efficient 3D decoupling capacitor solution for power management on silicon interposer

Guiller

Joblot

Lamy

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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First part of this paper discusses decoupling method limitation within the Power Delivery Network of a classical circuit and challenges introduced by 3D integrated circuit in term of power management. Solutions are exposed, such as integration of decoupling capacitor on silicon interposer.Second part of the paper focuses on the Through Silicon Capacitor (or TSC) as an alternative decoupling solution cointegrated with Through Silicon Vias on silicon interposer. TSC realization is described and architectural benefits of adding a partial copper-filling prior to the Metal-InsulatorMetal stack deposition are discussed.A distributed analytical model is used to quantify partial filling resistance contribution, pointing out a 6 decade decrease in ESR value of the structure. TSC process and matrix design parameters impact on capacitance density are studied. Finally, electrical performances of TSC modules are evaluated showing a low intrinsic impedance behavior granted by TSC parallel structure.

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“…Here, we use a physically based frequency-dependent compact analytical MIM capacitor model based on a planar structure. The decap model is expressed as a complex impedance formula [16] and Fig. 5 shows a description of the planar capacitor structure The complex impedance formula is expressed in real and imaginary parts, where the real term represents the total series resistance and the imaginary term represents the total capacitance.…”

Section: Mim Decap Description and Simulation Approachmentioning

confidence: 99%

A Multitier Study on Various Stacking Topologies of TSV-Based PDN Systems Using On-Chip Decoupling Capacitor Models

Charles

Franzon

2015

IEEE Trans. Compon., Packag. Manufact. Technol.

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We studied the impedance characteristics of through-silicon via (TSV)-based power delivery networks (PDNs) for hierarchical on-die simulation and interconnect noise analysis. This paper compares the quality of power delivery in 3-D stacking scenarios for three distinct chip stacking topologies: 1) face-to-back (F2B); 2) face-to-face (F2F); and 3) back-to-back (B2B). Quantitatively, this paper compared the impedance noise level between the three stacking topologies and found the PDN impedance noise of F2F chip stacking to be relatively lower than F2B and B2B chip stacking topologies. A power delivery impedance below 1 for F2F chip stacking topology was possible up to 2 GHz. However, for F2B and B2B chip stacking, the PDN impedance could not get beyond sub-1 . The impedance was simulated between 0.1 and 20 GHz. Among power grid and power and ground TSV models presented in this paper, we also present and implemented a metal-insulatormetal capacitor model written as a complex impedance equation. With capacitor dimensions similar to the unit cell gird size (200 μm × 200 μm), the capacitance density (per unit area) ranged from 0.062 pF/μm 2 to 5.325 fF/μm 2 .Index Terms-Back-to-back (B2B), face-to-back (F2B), face-to-face (F2F), on-chip decoupling capacitors, power distribution network (PDN), segmentation method, through silicon via (TSV).

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Low-Frequency Series-Resistance Analytical Modeling of Three-Dimensional Metal–Insulator–Metal Capacitors

Cited by 10 publications

References 9 publications

A Novel High-Density Capacitor Design and Its Fabrication Technique Based on Selective Etching

A Novel High-Density Capacitor Design and Its Fabrication Technique Based on Selective Etching

Through Silicon Capacitor co-integrated with TSV as an efficient 3D decoupling capacitor solution for power management on silicon interposer

A Multitier Study on Various Stacking Topologies of TSV-Based PDN Systems Using On-Chip Decoupling Capacitor Models

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