Low-frequency noise measurements on <i>n</i>-InGaAs/<i>p</i>-InP junction field-effect transistor structures

Kugler, S.; Steiner, Klaus; Seiler, U.; Heime, K.; Kuphal, E.

doi:10.1063/1.99066

Cited by 11 publications

(5 citation statements)

References 12 publications

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“…So, it is likely that peaks Eb1 and Eb2 are related to levels in the InGaAs layer and are similar to the midgap states found in In 0.53 Ga 0.47 As material. [22][23][24] The activation energy and the apparent capture cross-section of trap Eb2 were evaluated to E C -0.37 6 0.01 eV and r na ¼ 2.0 6 0.4 Â 10 À15 cm 2 . For trap Eb1, the activation energy moves from E C -0.38 eV to E C -0.46 eV when the reverse bias changes from -0.1 V to -1.5 V (with V P ¼ 3 V) and the apparent capture cross-section remains at r na ¼ 4.0 6 4 Â 10 À15 cm 2 .…”

Section: Dlts Analysismentioning

confidence: 99%

Electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP

Ferrandis

Billaud

Duvernay

et al. 2017

Journal of Applied Physics

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To overcome the Fermi-level pinning in III-V metal-oxide-semiconductor capacitors, attention is usually focused on the choice of dielectric and surface chemical treatments prior to oxide deposition. In this work, we examined the influence of the III-V material surface cleaning and the semiconductor growth technique on the electrical properties of metal/Al 2 O 3 /In 0.53 Ga 0.47 As capacitors grown on InP(100) substrates. By means of the capacitance-voltage measurements, we demonstrated that samples do not have the same total oxide charge density depending on the cleaning solution used [(NH 4) 2 S or NH 4 OH] prior to oxide deposition. The determination of the interface trap density revealed that a Fermi-level pinning occurs for samples grown by metalorganic chemical vapor deposition but not for similar samples grown by molecular beam epitaxy. Deep level transient spectroscopy analysis explained the Fermi-level pinning by an additional signal for samples grown by metalorganic chemical vapor deposition, attributed to the tunneling effect of carriers trapped in oxide toward interface states. This work emphasizes that the choice of appropriate oxide and cleaning treatment is not enough to prevent a Fermi-level pinning in III-V metal-oxide-semiconductor capacitors. The semiconductor growth technique needs to be taken into account because it impacts the trapping properties of the oxide.

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Section: Dlts Analysismentioning

confidence: 99%

Electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP

Ferrandis

Billaud

Duvernay

et al. 2017

Journal of Applied Physics

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“…Average thermal velocity vth and effective density of states Ddos of ntype In0.53Ga0.47As at room temperature (300K) was considered to be 5.6×10 7 cms -1 and 2.2×10 17 cm -3 respectively from literature [48]. Though the value of capture cross section of In0.53Ga0.47As is still a matter of ongoing research, some reported values are between 7×10 -15 and 5×10 -17 cm 2 from deep level transient spectroscopy measurement [53][54][55] [56]. As error in σ does not inflict any major impact on ET, here we assumed it to be 1×10 -16 cm 2 which is also in range from the reported values [24].…”

Section: Results Discussionmentioning

confidence: 99%

Comprehensive Analysis of Quantum Mechanical Effects of Interface Trap and Border Trap Densities of High-k Al₂O₃/In_0.53Ga_0.47As on a 300-mm Si Substrate

Amir

Kim

2020

IEEE Access

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We investigated the effects of quantum confinement in determining the interface traps (Dit) and border traps (Nbt) of ALD deposited Al2O3 with temperature variations onto InxGa1-xAs on a 300mm Si (001) substrate. We also analysed the impact of these effects on the total gate capacitance of highk/Si and high-k/InxGa1-xAs structures using 1D Poisson-Schrodinger solver simulation tool (Nextnano). While quantum confinement has no or very little impact on the gate capacitance of high-k/Si structure, it has a considerably high amount of impact on the high-k/InxGa1-xAs structures and substantially lowers the total gate capacitance. To reflect the actual thickness between the insulator-semiconductor interface and charge centroid, capacitance-equivalent-thickness was used to reflect the effects of quantum confinement in the InxGa1-xAs layer. The Dit and Nbt values extracted using capacitance-equivalent-thickness were observed to be around 10% and 25%, respectively, higher than the values of extraction with equivalent-oxidethickness. INDEX TERMS Interface trap density, border trap density, quantum mechanical effect, high-k, III-V substrate.

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“…Lattice-matched epitaxy of n-type In 0.53 Ga 0.47 As on InP substrates by liquid phase epitaxy [1,2], molecular beam epitaxy (MBE) [3,4] or metal organic chemical vapor deposition [4] gives rise to a number of grown-in point defects, which are determined by the growth conditions [5], i.e. the III/V ratio, the doping density, etc.…”

Section: Introductionmentioning

confidence: 99%

Deep levels in metal–oxide–semiconductor capacitors fabricated on n-type In_0.53Ga_0.47As lattice matched to InP substrates

Simoen

Hsu

Alian

et al. 2019

Semicond. Sci. Technol.

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In this work, deep levels present in n-type In 0.53 Ga 0.47 As hetero-epitaxial layers grown latticematched on n-type InP substrates by molecular beam epitaxy have been studied by deep-level transient spectroscopy (DLTS). Metal-oxide-semiconductor capacitors are employed, based on an Al 2 O 3 gate oxide. It is shown that a single, near mid-gap electron trap dominates the DLTspectra, whatever the surface pre-or post-gate oxide deposition treatment. At the same time, it is shown that the deep level parameters vary significantly from capacitor to capacitor and from wafer to wafer. Only after Forming Gas Annealing, a stable value for the activation energy of 0.39±0.01 eV is obtained. These results are tentatively interpreted in terms of antisite defects in the epitaxial layer, which form a family of related complexes with close deep-level parameters.

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Low-frequency noise measurements on n-InGaAs/p-InP junction field-effect transistor structures

Cited by 11 publications

References 12 publications

Electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP

Electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP

Comprehensive Analysis of Quantum Mechanical Effects of Interface Trap and Border Trap Densities of High-k Al₂O₃/In_0.53Ga_0.47As on a 300-mm Si Substrate

Deep levels in metal–oxide–semiconductor capacitors fabricated on n-type In_0.53Ga_0.47As lattice matched to InP substrates

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Low-frequency noise measurements on n-InGaAs/p-InP junction field-effect transistor structures

Cited by 11 publications

References 12 publications

Electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP

Electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP

Comprehensive Analysis of Quantum Mechanical Effects of Interface Trap and Border Trap Densities of High-k Al2O3/In0.53Ga0.47As on a 300-mm Si Substrate

Deep levels in metal–oxide–semiconductor capacitors fabricated on n-type In0.53Ga0.47As lattice matched to InP substrates

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Product

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Comprehensive Analysis of Quantum Mechanical Effects of Interface Trap and Border Trap Densities of High-k Al₂O₃/In_0.53Ga_0.47As on a 300-mm Si Substrate

Deep levels in metal–oxide–semiconductor capacitors fabricated on n-type In_0.53Ga_0.47As lattice matched to InP substrates