Low D/sub it/, thermodynamically stable Ga/sub 2/O/sub 3/-GaAs interfaces: fabrication, characterization, and modeling

Passlack, M.; Hong, M.; Mannáerts, J. P.; Opila, R. L.; Chu, S. N. G.; Moriya, N.; Ren, F.; Kwo, J.

doi:10.1109/16.557709

Cited by 170 publications

(64 citation statements)

References 24 publications

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“…This mixture comes not from oxidation but from UHV deposition (e.g. Passlack, et al 1997;Hong et al, 2007;Passlack et al, 2007). Practically almost all papers of Passlack's team from the last twenty years have described oxide structures this type: Ga 2 O 3 (Gd 2 O 3 ) which were made in UHV apparatus.…”

Section: Metal Oxide Semiconductor Devicesmentioning

confidence: 99%

Wet Thermal Oxidation of GaAs and GaN

Korbutowicz¹,

Prazmowska²

2010

Semiconductor Technologies

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Section: Metal Oxide Semiconductor Devicesmentioning

confidence: 99%

Wet Thermal Oxidation of GaAs and GaN

Korbutowicz¹,

Prazmowska²

2010

Semiconductor Technologies

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“…3 is commonly observed 2,18,19 in III-V MOS structures. While possibly attributable to a low resistivity interfacial region of the oxide which reduces the effective oxide thickness and thus increases the apparent capacitance at low measurement frequencies (Maxwell-Wagner effect 18 ), it is in general not well understood. Using bias-dependent swept-frequency impedance spectroscopy, a total interface state density of 8x10 11 cm -2 has previously been found for the 110 nm oxide on n-type GaAs.…”

mentioning

confidence: 99%

“…Figure 3 shows 100 kHz high-frequency (CH) and quasi-static (CQ) capacitance-voltage measurements for the 17 nm oxides on both n-type and p-type GaAs under standard microscope illumination as is required for wide bandgap semiconductors due to the low thermal generation rate of electron-hole pairs. 18 The clear existence of three operational regimes -accumulation, depletion and inversion -of these MOS structures for both n-and p-type samples indicates that the Fermi level is unpinned. 6 Thicker oxides (48 nm and 110 nm) on both types of GaAs also show similar unpinned behavior (not shown).…”

mentioning

confidence: 99%

Electrical properties of InAlP native oxides for metal–oxide–semiconductor device applications

Cao

Zhang

et al. 2005

Applied Physics Letters

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Data are presented on the insulating properties and capacitance-voltage (CV) characteristics of metal-oxide-semiconductor (MOS) device-thickness (below ~100 nm) native oxides formed by wet thermal oxidation of thin InAlP epilayers lattice matched to GaAs. Low leakage current densities of J=1.4 x 10 -9 A/cm 2 and J=8.7 x 10 -11 A/cm 2 are observed at an applied field of 1 MV/cm for MOS capacitors fabricated with 17 nm and 48 nm oxides, respectively. TEM images show that the In-rich interfacial particles which exist in 110 nm oxides are absent in 17 nm oxide films. Quasi-static capacitance-voltage measurements of MOS capacitors fabricated on both n-type and p-type GaAs show that the InAlP oxide-GaAs interface is sufficiently free of traps to 1 support inversion, indicating an unpinned Fermi level. These data suggest that InAlP native oxides may be a viable insulator for GaAs MOS device applications. 2Due to the wide array of high electron mobility alloys of varying bandgaps that can be epitaxially grown on its surface, GaAs remains the most widely used semiconductor for high-speed electronic applications. While Schottky gates are commonly used in high-speed GaAs transistors, the restricted forward bias (a few tenths of a volt) that can be applied without excessive gate leakage currents limits their power handling capability.The electrical characteristics of native oxides of GaAs are far inferior to those of SiO 2 on Si, and an alternative insulator has long been pursued 1,2 to enable the preferred metal-insulator-semiconductor gate structure. Many deposited insulator/GaAs structures have been investigated, although only a few have yielded promising results. 3-6 Native oxide films on GaAs can offer advantages of processing convenience and low cost.Wet thermal oxides of AlGaAs 7 have been studied but found to suffer from midgap traps caused by residual interfacial As. 8 These traps lead to increased interface recombination velocity 9,10 and high leakage currents. 11 However, the wet thermal oxides of As-free As shown in the bright-field TEM images of Fig. 2, dark particles exist near the oxide/GaAs interface in the 110 nm oxide of Fig. 2 (a), while no dark interfacial particles appear in the 17 nm oxide of Fig. 2 (b). Fig. 2 (b) is representative of the entire observable area for this and a second wedge-polished cross section specimen, with the absence of particles also confirmed for plan-view specimens (not shown) in which possible loss of particles due to ion milling and electron beam interactions is suppressed by the fact that they are protected from the vacuum by the substrate and overlying oxide film. The interfacial particles in Fig. 2 (a) are believed to be indium rich based on Z-contrast TEM images 16 (not shown) and Auger depth profiling. 17 The size of the particles increases with the progressive consumption of the InAlP epilayer during oxidation. 16 We hypothesize that In, the heaviest element in the structure, outdiffuses more slowly than the other alloy constituents and hence accumulates near the inter...

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“…The frequency dispersion (offset between CQ and CH curves in accumulation) seen in Figure 2.12 is commonly observed 8,34,35 in III-V MOS structures. Possibly attributable to a high density of interface states or a low resistivity interfacial region of the oxide, which reduces the effective oxide thickness and thus increases the apparent capacitance at low measurement frequencies (Maxwell-Wagner effect 34 ), it is in general not well understood. Using bias-dependent swept-frequency impedance spectroscopy, a total interface state density of 8x10 11 cm -2 has previously been found for the 110 nm oxide on n-type GaAs.…”

Section: Ellipsometric Characterization Of Inalp Wet Oxidesmentioning

confidence: 75%

“…At the same field strength, the 48 nm nm oxides on both n-type and p-type GaAs under standard microscope illumination as is required for wide bandgap semiconductors due to the low thermal generation rate of electron-hole pairs. 34 The clear existence of three operational regimesaccumulation, depletion and inversion -of these MOS structures for both n-and ptype samples indicates that the Fermi level is unpinned. Thicker oxide (110 nm) on both types of GaAs also shows similar unpinned behavior (not shown).…”

Section: Ellipsometric Characterization Of Inalp Wet Oxidesmentioning

confidence: 96%

Electronic Properties and Device Applications of III-V Compound Semiconductor Native Oxides

Hall¹,

Fay²,

Kosel³

et al. 2006

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Executive Summary of AccomplishmentsOur research project entitled "Electronic Properties and Device Applications of III-V Compound Semiconductor Native Oxides" was focused primarily on developing and understanding InAlP wet thermal native oxides for GaAs-based electronic devices and yielded the following notable results:• First demonstration of microwave-frequency operation of a GaAs metal-oxidesemiconductor field-effect transistor (MOSFET) fabricated using wet thermal oxidization of InAlP lattice-matched to GaAs to form a native oxide gate insulator. For 1-µm gate length devices, a cutoff frequency (f t ) of 13.7 GHz and a maximum frequency of oscillation (f max ) of 37.6 GHz were obtained [1].• Follow-on use --Technology Assist: Notre Dame has negotiated a collaborative research agreement with RF Micro Devices, Inc. (Greensboro, NC) to investigate potential of III-V compound semiconductor native oxides for commercial GaAs-based MOSFET devices.• First demonstration of scalability of InAlP to thinner (~10-20 nm) films more suitable for devices, maintaining excellent insulating and unpinned interface properties. Extremely low leakage current densities observed even for these device-thickness films, with values comparable and often lower than that of other candidate GaAs gate dielectrics [2].• First reported III-V metal-oxide-semiconductor field-effect transistor (MOSFET) device utilizing native oxide of InAlP as the gate insulator [3].• Observation via Transmission Electron Microscopy (TEM) imaging that interfacial precipitates, which decrease in size with decreasing oxidation time, are completely absent in ~20 nm thick oxide films. Identification of precipitates as In rich [2, 6].• Development of new variable-temperature impedance spectroscopy measurement technique to determine low total interface state density of D it = 8 x 10 11 cm -2 for a 110 nm thick InAlP native oxide film. Trap activation energies were found (E a =0.17 eV from bias-dependent impedance spectra, 0.40 eV from measurements of temperaturedependent impedance spectra [4, 7].• Identification via transmission electron microscopy analysis in diffusion marker experiment of inward growth of InAlP native oxide, key to achieving electrically clean oxide/semiconductor interfaces [5].• Determination of InAlP native oxide bandgap (≥ 4.0 eV) and optical constants [2, 6].• Determination of mass density of InAlP native oxide films via X-ray reflectivity measurements. The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing the burden, to the Department of Defense, Executive Services and Communications Directorate (0704-0188). Respondents should be aware that notwithstanding any other provision of...

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Low D/sub it/, thermodynamically stable Ga/sub 2/O/sub 3/-GaAs interfaces: fabrication, characterization, and modeling

Cited by 170 publications

References 24 publications

Wet Thermal Oxidation of GaAs and GaN

Wet Thermal Oxidation of GaAs and GaN

Electrical properties of InAlP native oxides for metal–oxide–semiconductor device applications

Electronic Properties and Device Applications of III-V Compound Semiconductor Native Oxides

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