Low CTE &amp; High Elastic Modulus Substrate for Semiconductor Packaging.

Takano, Nozomu; Fukuda, Tomio; Ose, Masahisa; Murai, Hikari

doi:10.5104/jiep.3.210

Cited by 5 publications

(3 citation statements)

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“…And soft segments of the new resin system lead to the ultra low CTE and low residual stress. Moreover, the resin system contains higher amount of inorganic filler to attain ultra low CTE and high modulus by applying the FICS (filler interphase control system) technology [2][3][4]. …”

Section: Molecular Design Of New Resin Systemmentioning

confidence: 99%

Ultra low CTE (1.8 ppm/°C) core material for next generation thin CSP

Kotake

Murai

Takanezawa

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Along with the advancement in miniaturizing of mobile devices, typified by smart phones and tablet PCs, the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. As one of the most innovative solutions, the PoP (package on package) technology, which has the three-dimensional construction, has been expanding rapidly in recent years.However, the thinner PKG such as PoP tends to warp at the assembly process and cause the decrease in the connection reliability. Therefore ultra low CTE (coefficient of thermal expansion) core materials have been needed as a key solution for the reduction of the warpage for PoP.Recently, we have developed new ultra low CTE core material named E-770G for next generation thin CSP, applying new resin systems, featuring low shrinkage and low residual stress. In particular, E-770G has achieved ultra low CTE of 1.8 ppm/°C which leads to significant reduction of the warpage. Furthermore, it has low dissipation factor at high frequencies (Df: 0.005 at 1 GHz). So it's also applicable to high speed PKG applications.Confirming the warpage property, we evaluated the warpage behavior of the bottom PKG before/after assembly process. E-770G showed the much lower warpage than the conventional ultra low CTE core material.

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Section: Molecular Design Of New Resin Systemmentioning

confidence: 99%

Ultra low CTE (1.8 ppm/°C) core material for next generation thin CSP

Kotake

Murai

Takanezawa

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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“…FICS is a filler treating system that will efficiently afford a unique function at the filler surfaces [1][2][3].…”

Section: Filler Interphase Control Systemmentioning

confidence: 99%

Newly developed ultra low CTE materials for thin core PKG

Miyatake

Murai

Takanezawa

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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To achieve the recent improvements in miniaturization and performance of mobile devices (Smart phone, Tablet PC etc.), the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. However, the thinner PKG substrate may cause poor connection reliability due to increased warpage by soldering. The ultra low CTE (Coefficient of thermal expansion) core material has been required as the key solution for the reduction of the warpage of the thinner PKG substrate such as PoP (Package on package).We have just developed two types of ultra low CTE core materials named E-705G and E-800G to meet with the requirement, applying our original resin systems and the filler surface treatment technologies.The developed materials show the ultra low CTE(X,Y) property (2.8-3.3 ppm/ o C) similar to that of glass fabric itself. Also E-705G has high flexural modulus over 33-36 GPa at room temperature. Regarding E-800G, it has the good dielectric characteristics (lower dielectric constant and dissipation factor), can be applicable higher speed PKG. Both of the materials have high reliability and high heat resistance which is suitable for the lead-free soldering process.Confirming the warpage property, we evaluated the warpage behavior of PoP (bottom) constructions before/after assembly process. The newly developed materials showed the much lower warpage than the conventional low CTE material.

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“…Insulation materials used were E-679F and LX-67Y of Hitachi Chemical. E-679F is a high-Tg epoxy multilayer material for packaging substrates [5]; LX-67Y is a low dissipation factor (Df) multilayer material for high frequency applications [6]. The curing conditions of E-679F and LX-67Y are 60 min / 180 ºC / 4.0 MPa and 70 min / 230ºC / 3.0MPa, respectively.…”

Section: Coppermentioning

confidence: 99%

Profile-Free Copper Foil for High-Density Packaging Substrates and High-Frequency Applications

Ogawa

Onozeki

Moriike

et al. 2005

Proceedings Electronic Components and Technology, 2005. ECTC '05.

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A new profile-free copper foil has been developed whose surface roughness is Rz <1.5 µm with satisfactory adhesion strength. An original surface treatment provided affords good peel strength (0.7 kN/m or more) equivalent to that for the conventional roughened foil with sufficient reliability. With the new profile-free copper foil, the conventional subtractive method is applicable to the wiring of 60 µm pitch or less, and the short-circuit fault of electroless Ni/Pd/Au plating that is prone to occur in fine wiring could be restrained since the wiring is formed on a smooth surface. Moreover, the transmission loss at 5 GHz band will decrease by 8 dB/m since the surface roughness of the conductor line is suppressed. IntroductionThe amount of production of the high density multilayer printed wiring boards (PWBs) is increasing every year, since various kinds of electronic equipment are required to be downsized and light-weighted. PWBs are required to have higher wiring density and thinner insulation layer [1]-[3] ; the wiring line and space width for substrate applications are expected to became 10-20 µm pitch by 2010. Demand for smaller size and higher electrical performance of electronic equipment is getting stronger; accordingly, higher density in wiring and reduction in the attenuation of high-speed signals are required for packaging substrates. However, in the subtractive process using the conventional copper foil with larger surface roughness (Rz > 7 µm), the foil is too rough to fabricate the wiring without short-circuit faults, because rough copper particles are difficult to etch. Even if lowprofile copper foil with Rz of 2-3µm is used, wiring pitch is limited to 50 µm. To meat the demand for such high density in wiring, a semi-additive method has been adopted, in which 60 µm pitch wiring is made possible. In the conventional semi-additive method, a process of roughing the surface of the insulating layer with chemicals is required, thus limiting the insulating layer to be used. The attenuation of high-speed signals is large on the whole for such insulating layers.In highly networked information society, signals will become larger in volume and higher in speed then the signal frequency used is expected to be over 10 GHz. High frequency signal current suffers the skin effect and will flow only the outer skin part (1-2 µm thick) of the conductor copper line. Roughen surfaces will then increase the line resistance at high frequencies. To suppress transmission losses, smoother surfaces have the advantage.

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Low CTE & High Elastic Modulus Substrate for Semiconductor Packaging.

Cited by 5 publications

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Ultra low CTE (1.8 ppm/°C) core material for next generation thin CSP

Ultra low CTE (1.8 ppm/°C) core material for next generation thin CSP

Newly developed ultra low CTE materials for thin core PKG

Profile-Free Copper Foil for High-Density Packaging Substrates and High-Frequency Applications

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Low CTE & High Elastic Modulus Substrate for Semiconductor Packaging.

Cited by 5 publications

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Ultra low CTE (1.8 ppm/&#x00B0;C) core material for next generation thin CSP

Ultra low CTE (1.8 ppm/&#x00B0;C) core material for next generation thin CSP

Newly developed ultra low CTE materials for thin core PKG

Profile-Free Copper Foil for High-Density Packaging Substrates and High-Frequency Applications

Contact Info

Product

Resources

About

Ultra low CTE (1.8 ppm/°C) core material for next generation thin CSP

Ultra low CTE (1.8 ppm/°C) core material for next generation thin CSP