Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors

Nicolaidis, M.; Pérez, Roc Berenguer; Alexandrescu, Dan

doi:10.1109/vts.2008.15

Cited by 70 publications

(63 citation statements)

References 6 publications

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“…As will be evaluated in section IV, the proposed design in [1,2] shows weak robustness in the presence of SEMUs. A soft error tolerant SRAM cell including 10 transistors is proposed in [9]. As can be seen in Figure 2b, this circuit exploits the same idea as [4,8] to prevent propagation of the transient effect caused by a particle strike.…”

Section: Previous Workmentioning

confidence: 99%

“…Therefore, providing the best trade-off between different parameters is an important design challenge. The reliability of memory cells is a major concern in safety-critical applications [9,13] as they hold vital information. For this reason, in this paper, we have promoted the reliability of the SRAM cells considering some emerging reliability issues in current VLSI designs including SEMUs and process variations.…”

Section: Comparative Analysesmentioning

confidence: 99%

“…A low area, high density. and soft error tolerant bit cell is of interest in many applications [9]. As another example, the proposed RAFT2 circuit has 189.4% lower power consumption and 74.75% lower PDP than the prominent DICE cell [7].…”

Section: Comparative Analysesmentioning

confidence: 99%

“…A similar scenario could repeat when the cell contains logic value of '0' (shown in Figure 9b). In cases in which the switch transistors are ON for a short time, energetic particle strikes could alter the stored value of the RATF1, RATF2, 10T [9], 11T [8], and 13T [4]. All these SRAM cells use the periodically ON/OFF feedbacks and hence they have some nodes that striking energetic particles could change the stored value of.…”

Section: Radiation Robustness In the Presence Of Single Event Upsetsmentioning

confidence: 99%

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Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

Rajaei¹,

Asgari²,

Tabandeh³

et al. 2017

Turk J Elec Eng & Comp Sci

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Abstract:In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs).Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75% lower PDP compared with DICE), much more soft error robustness, and larger noise margins.

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Section: Previous Workmentioning

confidence: 99%

Section: Comparative Analysesmentioning

confidence: 99%

Section: Comparative Analysesmentioning

confidence: 99%

Section: Radiation Robustness In the Presence Of Single Event Upsetsmentioning

confidence: 99%

See 2 more Smart Citations

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

Rajaei¹,

Asgari²,

Tabandeh³

et al. 2017

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

show abstract

“…Every store operation writes to both the RRAM and the SRAM; so, the SRAM core and the RRAM are monitored by the dual-rail checker. As also applicable to hardened memory cells found in the technical literature [80,81], the condition of logic inversion always applies to V DN and V D .Two cases are applicable. The outputs of the dual-rail checker also ensure that a single fault occurring in one of the XOR gates will be detected as generating an invalid code at the output, i.e.…”

Section: Dual-rail Checkermentioning

confidence: 99%

Design and modeling of nonvolatile memories by resistive switching elements

Junsangsri¹

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With the continued scaling in the nano ranges, the technology roadmap predicted by Moore's Law is becoming difficult to meet. So-called emerging technologies have been widely reported to supersede or complement CMOS. This type of design style is commonly referred to as "hybrid" because it exploits different characteristics of emerging technologies. This is very attractive for memories in which the modular (cell-based) organization of these systems is well suited to new technologies and innovative paradigms for design. This research presents new hybrid memory design which employ emerging technologies; such as memristor, phase change memory (PCM), programmable metallization cell (PMC), and racetrack memory (RM); and CMOS. By introduced new HSPICE macromodel of these emerging technologies and their memory applications such as the nonvolatile memory cell, CAM, TCAM, NVSRAM, and crossbar array, hybrid nonvolatile memory cells are generated. With its nonvolatile storage element, fast switching time, low power consumption, and good scalability, the hybrid memory cell of emerging technologies and CMOS would be one of the most promising candidates for the next generation of the nonvolatile memory.iii ACKNOWLEDGEMENTS

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Circuit-Level Soft-Error Mitigation

Nicolaidis

2010

Soft Errors in Modern Electronic Systems

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Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors

Cited by 70 publications

References 6 publications

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

Design and modeling of nonvolatile memories by resistive switching elements

Circuit-Level Soft-Error Mitigation

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