Low cost concurrent error detection for the advanced encryption standard

Wu, Kaijie; Karri, Ramesh; Kuznetsov, G.; Goessel, M.

doi:10.1109/test.2004.1387397

Cited by 99 publications

(91 citation statements)

References 5 publications

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“…To overcome the overhead due to the parity based concurrent checking, paper [34] describes the low-cost concurrent checking method.…”

Section: Attacks and Countermeasure (If Possible)mentioning

confidence: 99%

A Survey on Advanced Encryption Standard

2017

IJSR

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“…To overcome the overhead due to the parity based concurrent checking, paper [34] describes the low-cost concurrent checking method.…”

Section: Attacks and Countermeasure (If Possible)mentioning

confidence: 99%

A Survey on Advanced Encryption Standard

2017

IJSR

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“…They can be grouped into four categories: information redundancy, time redundancy, hardware redundancy, and hybrid redundancy. Information redundancy can for example be achieved by adding parity bits [9], [25] (Fig. 1(a)) or by a robust code ( Fig.…”

Section: B Concurrent Error Detection (Ced) Schemesmentioning

confidence: 99%

Fault Sensitivity Analysis Meets Zero-Value Attack

Mischke

Moradi

Güneysu

2014

2014 Workshop on Fault Diagnosis and Tolerance in Cryptography

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Abstract-Previous works have shown that the combinatorial path delay of a cryptographic function, e.g., the AES S-box, depends on its input value. Since the relation between critical path delay and input value seems to be relatively random and highly dependent on the routing of the circuit, up to now only template or some collision attacks could reliably extract the used secret key of implementations not protected against fault attacks. Here we present a new attack which is based on the fact that, because of the zero-to-zero mapping of the AES Sbox inversion circuit, the critical path when processing the zero input is notably shorter than for all other inputs. Applying the attack to an AES design protected by an state-of-the-art fault detection scheme, we are able to fully recover the secret key in less than eight hours. Note that we neither require a known key measurement step (template case) nor a high similarity between different S-box instances (collision case). The only information gathered from the device is whether a fault occurred when processing a chosen plaintext.

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“…Mainly, two approaches have been developed: based on information redundancy (e.g. the use of codes, [1] [2] [3]) or functional redundancy ( [3] [4] [5]). …”

Section: Introductionmentioning

confidence: 99%

“…As a consequence, the parity prediction requires larger circuitry. Solutions based on parity codes ( [1] [2]) lead to an overhead of about 20% and high single error detection. However they are not effective in case of multiple faults or single faults that lead to an even number of errors.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard

et al. 2009

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International audienceThis paper presents an on-line self-test architecture for hardware implementation of the Advanced Encryption Standard (AES). The solution exploits the inherent spatial replications of a parallel architecture for implementing functional redundancy at low cost. We show that the solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, the architectural modification for on-line test does not weaken the device with respect to side-channel attacks based on power analysis

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Low cost concurrent error detection for the advanced encryption standard

Cited by 99 publications

References 5 publications

A Survey on Advanced Encryption Standard

A Survey on Advanced Encryption Standard

Fault Sensitivity Analysis Meets Zero-Value Attack

A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard

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