A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard

Natale, Giorgio Di; Doulcier, Marion; Flottes, Marie-Lise; Rouzeyre, Bruno

doi:10.1007/s10836-009-5106-6

Cited by 36 publications

(24 citation statements)

References 9 publications

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“…White light, laser beams, voltage glitches, and temperature control are possible manipulation means to perform fault attacks [10]. Existing countermeasures for fault attacks are primarily based on error detection or/and correction codes [11,12].…”

Section: Security Threats and Countermeasures In 2d Icsmentioning

confidence: 99%

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs

Dofe

Wang

et al. 2016

Proceedings of the 26th Edition on Great Lakes Symposium on VLSI

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New hardware security threats are identified in emerging threedimensional (3D) integrated circuits (ICs) and potential countermeasures are introduced. Trigger and payload mechanisms for future 3D hardware Trojans are predicted. Furthermore, a novel, network-on-chip based 3D obfuscation method is proposed to block the direct communication between two commercial dies in a 3D structure, thus thwarting reverse engineering attacks on the vertical dimension. Simulation results demonstrate that the proposed method effectively obfuscates the cross-plane communication by increasing the reverse engineering time by approximately 5× as compared to using direct through silicon via (TSV) connections. The proposed method consumes approximately one fifth the area and power of a typical network-on-chip designed in a 65 nm technology, exhibiting limited overhead.

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Section: Security Threats and Countermeasures In 2d Icsmentioning

confidence: 99%

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs

Dofe

Wang

et al. 2016

Proceedings of the 26th Edition on Great Lakes Symposium on VLSI

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“…The existing counter-measures can be classified as technological counter-measures (such as metal shield), redundancy-based counter-measures for error detection (e.g. [22][23][24]), detector-based counter-measures which focus on fault detection (e.g. [25,26]).…”

Section: Counter-measuresmentioning

confidence: 99%

Laser-Induced Fault Effects in Security-Dedicated Circuits

Beroulle

Candelier

Castro

et al. 2015

VLSI-SoC: Internet of Things Foundations

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Abstract. Lasers have become one of the most efficient means to attack secure integrated systems. Actual faults or errors induced in the system depend on many parameters, including the circuit technology and the laser characteristics. Understanding the physical effects is mandatory to correctly evaluate during the design flow the potential consequences of a laser-based attack and implement efficient counter-measures. This paper presents results obtained within the LIESSE project, aiming at defining a comprehensive approach for designers. Outcomes include the definition of fault/error models at several levels of abstraction, specific CAD tools using these models and new counter-measures well-suited to thwart laser-based attacks. Actual measures on components manufactured in the new 28 nm FDSOI technology are also presented.

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“…Parity check code is one of the simplest error detecting codes that can be used to detect single bit error and odd number of bit flips [25]. Its advantage is that it can be implemented with low hardware overhead [26]. Nicolaidis employed parity prediction and double rail checking together to devise a self-checking mechanism for ALUs and adders.…”

Section: Related Workmentioning

confidence: 99%

Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System

Amin

Shakir

Javed

et al. 2014

International Journal of Reconfigurable Computing

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We are proposing a design methodology for a fault tolerant homogeneous MPSoC having additional design objectives that include low hardware overhead and performance. We have implemented three different FT methodologies on MPSoCs and compared them against the defined constraints. The comparison of these FT methodologies is carried out by modelling their architectures in VHDL-RTL, on Spartan 3 FPGA. The results obtained through simulations helped us to identify the most relevant scheme in terms of the given design constraints.

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A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard

Cited by 36 publications

References 9 publications

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs

Laser-Induced Fault Effects in Security-Dedicated Circuits

Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System

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