Low-Cost and Programmable CRC Implementation Based on FPGA

Abstract

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with a small and constant resource utilization. The experimental results show that the resource utilization of proposed non-segmented architecture is 84.1% and 37.6% lower than those of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has a lower resource utilization by 83.9% and 8.9% compared wtih the two state-of-the-art architectures; meanwhile, the throughput and programmability are guaranteed. We made the source code available on GitHub[1].

Perancangan dan Implementasi Encoder dan Decoder CRC-8 untuk Pendeteksian Error pada Transmisi Data antar Perangkat IoT

“…Selain itu, dengan semakin meningkatnya pemanfaatan teknologi Internet-of-Things (IoT) di mana akurasi data pada komunikasi antar transmitter dan receiver merupakan hal yang penting, pemanfaatan kode pendeteksi kesalahan seperti CRC diperlukan untuk mendeteksi adanya error pada data yang ditransmisikan [7]. Oleh karena luasnya penggunaan CRC pada berbagai sistem komunikasi data mulai dari Universal Serial Bus (USB), Ethernet, komunikasi seluler, hingga IoT, penelitian yang berkaitan dengan algoritma perhitungan CRC untuk menghasilkan komputasi yang cepat dan efisien terus dilakukan [8]- [10] hingga saat ini, meskipun kode CRC telah ada sejak tahun 1960-an. Secara umum implementasi CRC banyak dilakukan pada perangkat keras (hardware) baik menggunakan Field Programmable Gate Array (FPGA) maupun Application-specific Integrated Circuit (ASIC).…”