Low cost and high throughput multiplierless design of a 16 point 1-D DCT of the new HEVC video coding standard

Jeske, Ricardo; Souza, José Cláudio de; Wrege, Gustavo; Conceição, Ruhan; Grellert, Mateus; Mattos, Júlio C. B.; Agostini, Luciano

doi:10.1109/spl.2012.6211786

Cited by 22 publications

(18 citation statements)

References 2 publications

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“…Table I shows the hardware overhead comparisons of our proposed 1-D Transformation core with other 1-D HEVC DCT/IDCT architectures. Thereinto, reference [6] and [5]'s architectures are implemented with FPGA, and the gate counts are their LUT numbers.…”

Section: Experimental Results and Performance Analysismentioning

confidence: 99%

“…According our evaluation, its hardware utilization is lower than 20%. According to the table, the hardware utilization rates of reference [6], reference [5] and reference [7] are much higher than others. However, the performance of these parallel architectures with huge throughput far exceed their practical requirements.…”

Section: 3mentioning

confidence: 93%

“…R. Jeske also presented a 16-point 1-D DCT multiplierless hardware architecture for HEVC in 2012 [5]. Based on approximation DCT algorithm, A. Edirisuriya proposed a multiplicationfree architecture for 16×16 point approximation HEVC 2-D DCT/DST transform in 2012 [6].…”

Section: Introductionmentioning

confidence: 99%

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A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

Hong

Zhu

et al. 2013

IEICE Electron. Express

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High Efficiency Video Coding (HEVC) is the currently developing video coding standard beyond H.264/AVC. In this paper, a full pipelined 2-D IDCT/IDST VLSI architecture compatible with HEVC standard is presented for the first time. The proposed architecture supports adaptive block size IDCT from 4×4 to 32×32 pixels as well as IDST while keeping nearly 100% hardware utilization. Using SMIC 65 nm 1P9M technology, the synthesis results show that the architecture achieves the maximum work frequency at 480 MHz and the hardware cost is about 115.8 K Gates. Experimental results show that the proposed architecture is able to deal with realtime HEVC IDCT/IDST of 4 K×2 K (4096×2048)@30 fps video sequence at 171 MHz in average. In consequence, it offers a costeffective solution for the future UHDTV applications.

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Section: Experimental Results and Performance Analysismentioning

confidence: 99%

Section: 3mentioning

confidence: 93%

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A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

Hong

Zhu

et al. 2013

IEICE Electron. Express

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“…Of course, some fast algorithm can be adopted to narrow down the range of traversal. But according to these state-of-art techniques [5] [6] [7], the remaining range is still wide, leading to still-huge calculation amount, which gives rise to many high-throughput DCT designs [8] [9] [10].…”

Section: A Dct/idct In Hevcmentioning

confidence: 99%

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs

Fan

Huang

Bai

et al. 2015

IEEE Trans. Circuits Syst. II

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In the high efficiency video coding (HEVC) standard, a notation of transform unit (TU) is introduced with 4 different sizes, i.e. 4×4, 8×8, 16×16 and 32×32, which results in at least two problems in the use of discrete cosine transform/inversed discrete cosine transform (DCT/IDCT). One is changeable input/output (I/O) format presented by DCT/IDCT when it deals with TUs of different sizes, which intensifies the inconformity during the data exchange with other modules. The other is the demand for high throughput to traverse the vast possible TU partitions to find the best one, which would be easily dragged by an inefficient data exchange method. To solve this problem, a parallel-access data mapping method based on single-port SRAMs is proposed in this paper. It can be applied to the data exchange buffers around DCT/IDCT in HEVC encoders to fulfill a high-throughput data exchange. Here, parallel-access means 1 row of 1×32 pixels, 2 rows of 1×16 pixels, 4 rows of 1×8 pixels or 4 rows of 1×4 pixels could be accessed in one cycle depending on the specific size of current TU.Index Terms-data mapping method, buffer, discrete cosine transform (DCT), inversed discrete cosine transform (IDCT), high efficiency video coding (HEVC), single-port SRAM

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“…Hardware encoders apply a number of parallelisation techniques to satisfy real-time requirements. In the literature, there are some architectures developed to accelerate the DCT/IDCT (inverse DCT) computation for H.265/HEVC [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. Some of them do not support all transform sizes [10-12, 14, 18, 20].…”

Section: Introductionmentioning

confidence: 99%

Hardware architectures for the H.265/HEVC discrete cosine transform

Pastuszak

2015

IET Image Processing

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This study presents a design methodology for the two-dimensional (2D) discrete cosine transform dedicated for H.265/ HEVC hardware encoders. The methodology decomposes matrix multiplications for different transform sizes into some steps based on the division of transform units into fixed-size blocks. The modified order of processed blocks allows a significant reduction of the size of the transposition buffer. As a consequence, the resource consumption of the whole 2D-transform architecture is decreased. Separate transform cores assigned to two transform stages increase the throughput more than twice. The decomposition enables different hardware configurations of the architectures. Particularly, the architectures applying the proposed methodology are parametrically specified in VHDL, and configuration parameters enable the tradeoff between resources and the throughput. Furthermore, the interface adaptation to desired horizontal and vertical sizes is possible. The use of regular multipliers allows the support for transforms specified in other video standards. Computational elements embedded in architectures are well-suited to FPGA devices, which improves the area-speed efficiency. Synthesis results show that they can operate at 200 and 400 MHz when implemented in FPGA Arria II and TSMC 90 nm, respectively.

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Low cost and high throughput multiplierless design of a 16 point 1-D DCT of the new HEVC video coding standard

Cited by 22 publications

References 2 publications

A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs

Hardware architectures for the H.265/HEVC discrete cosine transform

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