Low cost 65nm CMOS platform for Low Power &amp;amp; General Purpose applications

Arnaud, F.; Duriez, B.; Tavel, B.; Pain, Laurent; Todeschini, J.; Jurdit, M.; Laplanche, Y.; Bœuf, F.; Salvetti, F.; Lenoble, D.; Reynard, J. P.; Wacquant, F.; Morin, Pascal; Emonet, N.; Barge, D.; Bidaud, M.; Ceccarelli, Daniele; Vannier, P.; Loquet, Yannick; Leninger, H.; Judong, F.; Perrot, C.; Guilmeau, I.; Palla, R.; Beverina, A.; DeJonghe, V.; Broekaart, M.; Vachellerie, V.; Bianchi, R.A.; Borot, B.; Devoivre, T.; Bicais, N.; Roy, Debapriya Basu; Denais, M.; Rochereau, K.; Difrenza, R.; Planes, N.; Brut, H.; Vishnobulta, L.; Reber, D.; Stolk, P. A.; Woo, M.

doi:10.1109/vlsit.2004.1345363

Cited by 25 publications

(13 citation statements)

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“…When special test structures are used to access exclusively the intrinsic parameter fluctuations, it is practically impossible to separate the individual contributions of different intrinsic-parameter-fluctuation sources. In Table III, we compare σV T resulting with combined action of RDD, LER, and OTV with recent data published in [39], [40]. In all cases, in order to scale the data for square 35 × 35 nm transistors, we have assumed that σV T ∝ 1/ √ LW .…”

Section: Resultsmentioning

confidence: 99%

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

Roy

Brown

Adamu-Lema

et al. 2006

IEEE Trans. Electron Devices

264

117

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Abstract-In this paper, using three-dimensional statistical numerical simulations, the authors study the intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness (LER), and oxide-thickness variations in realistic bulk MOSFETs scaled to 25, 18, 13, and 9 nm. The scaling is based on a 35 nm MOSFET developed by Toshiba, which has also been used for the calibration of the authors' "atomistic" device simulator. Special attention is paid to the accurate resolution of the individual discrete dopants in the drift-diffusion simulations by introducing density-gradient quantum corrections for both electrons and holes. In the LER simulations, two scenarios have been adopted: In the first one, LER follows the prescriptions of the International Roadmap for Semiconductors; in the second one, LER is kept constant close to the current best values. Combined effects of the different sources of intrinsic parameter fluctuations have also been simulated in the 35 nm reference devices and the results for the standard deviation of the threshold voltage compared to the measured values.

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Section: Resultsmentioning

confidence: 99%

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

Roy

Brown

Adamu-Lema

et al. 2006

IEEE Trans. Electron Devices

264

117

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“…We conduct g maximum overlay n the M1 layer, and uit after parasitic ay and read/write inations of CD and ad/write delay was n read/write margin rinting M1, overlay rs for choosing one s should be on ease of cell area. Since pact on delay and niques that exhibit erence [19] presents M cell in 65nm, and considered to be a e M1 layer using Pby side. Layout el (a single cell is y introducing a few when we consider r image of the cell a tip to tip distance cells.…”

Section: Metal 1 Layermentioning

confidence: 99%

Design-patterning co-optimization of SRAM robustness for double patterning lithography

Joshi

Agarwal

Sylvester

2012

17th Asia and South Pacific Design Automation Conference

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Double patterning lithography (D attractive optical lithography solution for 32n technology nodes. There are two primary pitch-split double patterning (PSDP) and se patterning (SADP), which can be implemente tone or a negative tone process. Each DPL im a different impact on line space and linewidth analyzing the impact of these different DPL overall process flow can be achieved. This comprehensive analysis and optimization compares the layerwise impact of different SRAM robustness, density, and printability. I sizing optimization that accounts for increas to DPL for each layer. Experimental result industrial models show that using the best DP layer, along with the sizing optimization p achieve single exposure robustness togethe DPL printability at almost no overhead increase in write energy). Specifically, cell f can be further reduced by 5X as compar exposure failure probability, at the cost of energy by 6.3% and write delay by 2.5%.

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“…We use a 65-nm CMOS technology with LP/GP process mix for a total of 6 V t options [10]: GP LVT, GP SVT, GP HVT, LP LVT, LP SVT, and LP HVT, in increasing V t order. A reduced set of 97 cells is implemented in each V t option by CAD layer manipulations, each recharacterized in the 0.25-0.6-V V dd range by 10-mV steps with Synopsys Liberty NCX.…”

Section: Flow Tuning and Validationmentioning

confidence: 99%

“…Experimental results of the proposed flow for several ITC'99 benchmarks in a 65-nm CMOS with LP/GP process mix [10] with six different V t options are compared with exhaustive searches for the optimum (V, L, N ) solution. For f target values between 100 kHz and 30 MHz, the average E cycle overhead of the proposed flow is below 10%, while considerably speeding up the design phase.…”

Section: Introductionmentioning

confidence: 99%

A Fast ULV Logic Synthesis Flow in Many-$V_{t}$ CMOS Processes for Minimum Energy Under Timing Constraints

Bol

Hocquet²,

Regazzoni³

2012

IEEE Trans. Circuits Syst. II

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Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (V dd ) and threshold (V t ) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the V dd /V t MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all V dd /V t pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC'99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4× compared to a conventional flow with V dd scaling only.

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Low cost 65nm CMOS platform for Low Power & General Purpose applications

Cited by 25 publications

References 0 publications

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

Design-patterning co-optimization of SRAM robustness for double patterning lithography

A Fast ULV Logic Synthesis Flow in Many-$V_{t}$ CMOS Processes for Minimum Energy Under Timing Constraints

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