Low-Complexity Switch Network for Reconfigurable LDPC Decoders

Oh, Daesun; Parhi, Keshab K.

doi:10.1109/tvlsi.2008.2007736

Cited by 51 publications

(61 citation statements)

References 14 publications

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“…The proposed structure combines the structures of [3] and [9]: the input data are processed by a pre-rotator as in [3] and then the remaining shifts are performed by a few small Benes networks rather than a MUX-network. With this combination, the proposed structure can take advantage of both structures, that is, the efficiency of a Benes network and pre-rotation optimization.…”

Section: Low-complexity Multi-size Cyclic-shifter For Qc-ldpc Codesmentioning

confidence: 99%

“…1. Previous structures: (a) pre-rotator and MUX-network structure [3], (b) rotator-in-parallel structure [6], (c) rotator-in-series structure [7], and (d) Benes-network structure [9]. …”

Section: Multi-size Cyclic Shiftermentioning

confidence: 99%

“…In [9], the authors proposed a control signal generation scheme for the MSCS operation and a Benes network with 3 × 3 switches or 5 × 5 switches for the case when N = 3 × 2 n or N = 5 × 2 n . The 3 × 3 switch proposed in [9] consists of three 2 × 2 switches, as shown in Fig. 2(b).…”

Section: Prerotationmentioning

confidence: 99%

“…In the two equations, the first term in the parentheses is for the n stages of the 2 × 2 switches in the front and rear, and the second term is for the center stage of the 3 × 3 switches. The critical path of the 3 × 3 switch proposed in [9] includes three 2-to-1 MUXs. A faster 3 × 3 switch was proposed in [12], which has two 2-to-1 MUXs in the critical path.…”

Section: Prerotationmentioning

confidence: 99%

“…To support various sizes, two barrel rotators are placed in parallel [4], [6] or series [7]. The other kind is based on a Benes network, which can route any N × N permutation [8], [9]. A Benes network is efficient for permutation but inappropriate for optimization with rotation properties.…”

Section: Introductionmentioning

confidence: 99%

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Low-Complexity Multi-size Cyclic-Shifter for QC-LDPC Codes

Kang

Yang

2017

ETRI Journal

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The decoding process of a quasi-cyclic low-density parity check code requires a unique type of rotator. These rotators, called multi-size cyclic-shifters (MSCSs), rotate input data with various sizes, where the size is the amount of data to be rotated. This paper proposes a lowcomplexity MSCS structure for the case when the sizes have a nontrivial common divisor. By combining the strong points of two previous structures, the proposed structure achieves the smallest area. The experimental results show that the area reduction was more than 14.7% when the proposed structure was applied to IEEE 802.16e as an example.

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Section: Low-complexity Multi-size Cyclic-shifter For Qc-ldpc Codesmentioning

confidence: 99%

“…1. Previous structures: (a) pre-rotator and MUX-network structure [3], (b) rotator-in-parallel structure [6], (c) rotator-in-series structure [7], and (d) Benes-network structure [9]. …”

Section: Multi-size Cyclic Shiftermentioning

confidence: 99%

Section: Prerotationmentioning

confidence: 99%

Section: Prerotationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-Complexity Multi-size Cyclic-Shifter for QC-LDPC Codes

Kang

Yang

2017

ETRI Journal

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A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio

Pourjabar

Choi

2021

Circuit Theory & Apps

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This paper presents a partially parallel low-density parity-check (LDPC) decoder for the 5G New Radio (NR) standard. The design is using a multiblock parallel architecture with a flooding schedule. The decoder can support any code rates and code lengths up to the lifting size Z max = 96. To compensate for the dropped throughput associated with the smaller Z values, the design can double and quadruple its parallelism when lifting sizes Z ≤ 48 and Z ≤ 24 are selected, respectively. Therefore, the decoder can process up to eight frames and restore the throughput to the maximum. To facilitate the design's architecture, a new variable node for decoding the extended parity bits existing in the lower code rates is proposed. The FPGA implementation of the decoder results in a throughput of 2.1 Gbps decoding the 11/12 code rate. Additionally, the synthesized decoder using the 28-nm TSMC technology achieves a maximum clock frequency of 526 MHz and a throughput of 13.46 Gbps. The core decoder occupies 1.03 mm 2 , and the power consumption is 229 mW.

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