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A (full-complexity) per-survivor iterative timing recovery scheme, which jointly performs timing recovery, equalization, and error-correction decoding, was recently proposed [1] to deal with the problem of timing recovery operating at low signal-to-noise ratio. Although it outperforms other iterative timing recovery schemes, it has very high complexity. In this paper, we propose a reduced-complexity per-survivor iterative timing recovery scheme to make it implementable in real-life applications. Simulation results indicate that for low to moderate complexity, the reducedcomplexity scheme provides a better performance than the full-complexity scheme.

Abstract-A conventional receiver performs timing recovery and equalization separately. Specifically, conventional timing recovery is based on a phase-locked loop that relies on the decision provided by its own symbol detector. We propose a new timing recovery scheme based on per-survivor processing (PSP) that jointly performs timing recovery and equalization for uncoded partial response channels. In the proposed scheme, each survivor of the Viterbi algorithm maintains its own estimate of the timing offset, and this estimate is updated according to the history data associated with the survivor path. As compared to conventional timing recovery at BER = 10 −4 , the proposed scheme can provide a 0.5 dB gain in SNR.

For any given communication channel, it is desirable to recover all the initial timing information during acquisition and/or any phase and frequency changes during tracking as fast as possible. In this paper, we propose the oversampled per-survivor processing (PSP) timing recovery (TR) architecture to achieve fast convergence rate in the applications of magnetic recording channels. Its performance is compared with the symbol-rate PSP-based TR, the oversampled conventional TR (OCTR), and also with the symbolrate conventional TR (CTR) architecture used in today's magnetic recording read-channel chip architectures. Results indicate that the oversampled PSP (OPSP) TR yields the best bit-error rate (BER) performance among other TR architectures when fast convergence is required.

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