Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes

Oh, Daesun; Parhi, Keshab K.

doi:10.1109/sips.2006.352592

Cited by 15 publications

(9 citation statements)

References 10 publications

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“…Due to its widely dynamic range (up to +∞), the (x) function has a high complexity and is prone to quantization noise. Although many approximations have been proposed to improve the numerical accuracy of (x) [26,29,48], it is still expensive to implement the (x) function in hardware. However, the non-linear term in the f (·) function has a very small dynamic range:…”

Section: Map Functional Unit For Ldpc Codesmentioning

confidence: 99%

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A Flexible LDPC/Turbo Decoder Architecture

Sun

Cavallaro

2010

J Sign Process Syst

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Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm 2 . The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE

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Section: Map Functional Unit For Ldpc Codesmentioning

confidence: 99%

“…In the literature, many efficient LDPC decoder VLSI architectures have been studied [6,9,12,14,18,24,27,29,35,37,39,45,47]. Turbo decoder VLSI architectures have also been extensively investigated by many researchers [5,8,20,21,25,30,33,41,44].…”

Section: Introductionmentioning

confidence: 99%

A Flexible LDPC/Turbo Decoder Architecture

Sun

Cavallaro

2010

J Sign Process Syst

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“…Reduction in accuracy reduces complexity, but only at the cost of reduced decoding performance of the algorithm. Various schemes have been proposed in order to efficiently realize onto hardware, such as piece-wise linear approximation [25] or non-uniform quantization [26]. A way to compute (x) is to store it in a lookup table using a uniform quantization scheme [27].…”

Section: Impact Of Roundoff On Decisionsmentioning

confidence: 99%

Impact of Approximation Error on the Decisions of LDPC Decoding

Kanistras

Paliouras

2010

J Sign Process Syst

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In this paper the impact of the approximation error on the decisions taken by LDPC decoders is studied. In particular, we analyze the mechanism, by means of which approximation error alters the decisions of a finite-word-length implementation of the decoding algorithm, with respect to the decisions taken by the infinite precision case, approximated here by double-precision floating-point. We focus on four popular algorithms for LDPC decoding, namely Log Sum-Product, Min-Sum, normalized Min-Sum and offset Min-Sum. A corresponding theoretical model is developed which derives an expression for the probability of altering the decision due to approximation. The model is applied to the above algorithms for the case of the first iteration as well as for higher numbers of iterations. Finally, experimental results prove the validity of the proposed model.

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“…approximations have been studied to improve the numerical accuracy of Ψ(x) [14,15,16], it is still very expensive to implement it in hardware. However, the non-linear term in the f (·) function has a much lower dynamic range: 0 < g(x) log(1 + e −x ) < 0.7, and thus is numerically more robust and less sensitive to quantization noise.…”

Section: Look-up-table Approximation For Ldpc Decodingmentioning

confidence: 99%

Unified decoder architecture for LDPC/turbo codes

Sun

Cavallaro

2008

2008 IEEE Workshop on Signal Processing Systems

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Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon limit. However, their different code structures usually lead to different hardware implementations. In this paper, we propose a unified decoder architecture that is capable of decoding both LDPC and turbo codes with a limited hardware overhead. We employ maximum a posteriori (MAP) algorithm as a bridge between LDPC and turbo codes. We represent LDPC codes as parallel concatenated single parity check (PCSPC) codes and propose a group sub-trellis (GST) decoding algorithm for the efficient decoding of PCSPC codes. This algorithm achieves about 2X improvement in the convergence speed and is more numerically robust than the classical "tanh" algorithm. What is more interesting is that we can generalize a unified trellis decoding algorithm for LDPC and turbo codes based on their trellis structures. We propose a reconfigurable computation kernel for log-MAP decoding of LDPC and turbo codes at a cost of ∼15% hardware overhead. Small lookup tables (LUTs) with 9 entries of 2-bit data are designed to implement the log-MAP algorithm. Fixed point (6:2) simulation results show that there is negligible or nearly no performance loss by using this LUT approximation compared to the ideal case. The proposed architecture results in scalable and flexible datapath units enabling parallel decoding of LDPC/turbo codes.

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Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes

Cited by 15 publications

References 10 publications

A Flexible LDPC/Turbo Decoder Architecture

A Flexible LDPC/Turbo Decoder Architecture

Impact of Approximation Error on the Decisions of LDPC Decoding

Unified decoder architecture for LDPC/turbo codes

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