Low Complexity Design of High Speed Parallel Decision Feedback Equalizers

Oh, Daesun; Parhi, Keshab K.

doi:10.1109/asap.2006.43

Cited by 22 publications

(14 citation statements)

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“…A comparison of the complexity for -PAM is shown in Table 3. We observe that the DFFE still provides a significant reduction of complexity with respect to the DFE architectures [7,9]. (In -PAM, multiplication operations are achieved by using − 1 2-to-1 muxes.)…”

Section: Parallel-processing Dffe Architecturementioning

confidence: 96%

“…The existing parallel DFE architectures of [4,9,10] are faster than the DFFE. However, they are not considered for a speed comparison as a result of their prohibitive high implementation complexity in the presence of channels with high ISI ( ≫ 1).…”

Section: Analysis Of the Critical Pathmentioning

confidence: 99%

“…The number of adders for the DFFE was estimated assuming that the basic building block is a twoinput adder. Table 2 presents a comparison of the complexity of the DFFE with the DFE architectures proposed in [4,7,9,10]. The numbers of adders and 2-to-1 multiplexers for the parallel DFE schemes were extracted from [4,7,9], while the number of registers was estimated based on their architectures.…”

Section: Parallel-processing Dffe Architecturementioning

confidence: 99%

“…These architectures can mitigate the speed limitation of feedback loops by using nested multiplexer loops where the implementation is reported in [10]. Some further improvements to these schemes have been proposed in [8,9]. However, the implementation complexity of DFE parallel architectures based on look-ahead pipelined multiplexer loops still increases exponentially with the number of feedback taps.…”

Section: Introductionmentioning

confidence: 99%

“…Some algorithms to deal with the drawbacks of the DFE in high-speed applications and parallel processing have been proposed by [4][5][6][7][8][9][10][11][12]. For example, parallel DFE architectures based on look-ahead pipelined multiplexer loops have been introduced in [6,7].…”

Section: Introductionmentioning

confidence: 99%

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A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Pola

Cousseau

Agazzi³

et al. 2013

Journal of Electrical and Computer Engineering

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This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in the presence of highly dispersive channels. This decision-aided equalizer technique has been recently proposed for multigigabit communication receivers, where the use of parallel processing is mandatory. Well-known parallel architectures for the typical decision feedback equalizer (DFE) have a complexity that grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to cancel iteratively the intersymbol interference (ISI). Here, we demostrate that the DFFE not only allows to obtain a similar performance to the typical DFE but it also reduces the compelxity in channels with large memory. Additionally, we propose a theoretical approximation for the error probability in each iteration. In fact, when the number of iteration increases, the error probability in the DFFE tends to approach the DFE. These benefits make the DFFE an excellent choice for the next generation of high-speed receivers.

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Section: Parallel-processing Dffe Architecturementioning

confidence: 96%

Section: Analysis Of the Critical Pathmentioning

confidence: 99%