Low-Complexity and High-Speed Constant Multiplications for Digital Filters Using Carry-Save Arithmetic

Gustafsson, Oscar; Wanhammar, Lars

doi:10.5772/16081

Cited by 9 publications

(4 citation statements)

References 23 publications

(30 reference statements)

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“…When targeting software, the function to optimize is the number of additions [1]- [5]. When targeting ASICs or FPGAs, the functions to optimize are the overall area at the level of fulladders [1], [6], [7] or even gates [8] as well as the overall speed [9] or throughput [10]. These are only correlated to the number of additions and depth of the tree, as different additions in the tree will be of different sizes, hence different area and delay.…”

Section: Introductionmentioning

confidence: 99%

Table-Based versus Shift-And-Add Constant Multipliers for FPGAs

Dinechin

Filip

Kumm

et al. 2019

2019 IEEE 26th Symposium on Computer Arithmetic (ARITH)

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The multiplication by a constant is a frequently used operation. To implement it on Field Programmable Gate Arrays (FPGAs), the state of the art offers two completely different methods: one relying on bit shifts and additions/subtractions, and another one using look-up tables and additions. So far, it was unclear which method performs best for a given constant and input/output data types. The main contribution of this work is a thorough comparison of both methods in the main application contexts of constant multiplication: filters, signalprocessing transforms, and elementary functions. Most of the previous state of the art addresses multiplication by an integer constant. This work shows that, in most of these application contexts, a formulation of the problem as the multiplication by a real constant allows for more efficient architectures. Another contribution is a novel extension of the shift-and-add method to real constants. For that, an integer linear programming (ILP) formulation is proposed, which truncates each component in the shift-and-add network to a minimum necessary word size that is aligned with the approximation error of the coefficient. All methods are implemented within the open-source FloPoCo framework. 1 With FloPoCo version 4.1.2, try the command flopoco FPExp we=11 wf=53 and look in the produced VHDL for the signal absKLog2.

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Section: Introductionmentioning

confidence: 99%

Table-Based versus Shift-And-Add Constant Multipliers for FPGAs

Dinechin

Filip

Kumm

et al. 2019

2019 IEEE 26th Symposium on Computer Arithmetic (ARITH)

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“…In this work, we consider two-input adders only, although a similar approach should be applicable to e.g. carry-save adders [19][20][21] or ternary adders [22,23].…”

Section: Introductionmentioning

confidence: 99%

Using Transposition to Efficiently Solve Constant Matrix-Vector Multiplication and Sum of Product Problems

Sarband

Gustafsson

Garrido

2020

J Sign Process Syst

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In this work, we present an approach to alleviate the potential benefit of adder graph algorithms by solving the transposed form of the problem and then transposing the solution. The key contribution is a systematic way to obtain the transposed realization with a minimum number of cascaded adders subject to the input realization. In this way, wide and low constant matrix multiplication problems, with sum of products as a special case, which are normally exceptionally time consuming to solve using adder graph algorithms, can be solved by first transposing the matrix and then transposing the solution. Examples show that while the relation between the adder depth of the solution to the transposed problem and the original problem is not straightforward, there are many cases where the reduction in adder cost will more than compensate for the potential increase in adder depth and result in implementations with reduced power consumption compared to using sub-expression sharing algorithms, which can both solve the original problem directly in reasonable time and guarantee a minimum adder depth. Keywords Constant matrix multiplication (CMM) • Multiple constant multiplication (MCM) • Shift-and-add • Sum of products (SOP) • Minimum depth expansion algorithm.

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Section: Introductionmentioning

confidence: 99%

“…Different methods have been proposed for the design of carry-save adder (CSA) based FIR filters, including the use of CSAs for structural adders [11], [12]. However, more adders are required compared to multiplier blocks designed by CPAs for word lengths of coefficients larger than 9 bits [12]. Moreover, the use of the redundant carry-save representation The area optimization of SAs in transposed form FIR filters was first investigated by Faust and Chang in [13].…”

Section: Introductionmentioning

confidence: 99%

Efficient structural adder pipelining in transposed form FIR filters

Faust

Kumm

Chang

et al. 2015

2015 IEEE International Conference on Digital Signal Processing (DSP)

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Pipelining is a common method to implement high speed FIR filters. While the efficient pipelining of multiplications is well understood, no attention has been paid on the pipelining of structural adders so far. The delay of structural adders becomes crucial in high speed designs as they have the largest word size in non-truncated FIR filters and typically lie in the critical path. The common pipelining method results in an excessive overhead in registers when applied to the structural adders as many additional paths have to be delayed. An efficient method for pipelining structural adders using a partially redundant number representation is proposed in this paper. With a very little area overhead of 5.4%, the throughput of the structural adders can be doubled while a speedup factor of up to 7 can be achieved with an area overhead of 26.7%.

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Low-Complexity and High-Speed Constant Multiplications for Digital Filters Using Carry-Save Arithmetic

Cited by 9 publications

References 23 publications

Table-Based versus Shift-And-Add Constant Multipliers for FPGAs

Table-Based versus Shift-And-Add Constant Multipliers for FPGAs

Using Transposition to Efficiently Solve Constant Matrix-Vector Multiplication and Sum of Product Problems

Efficient structural adder pipelining in transposed form FIR filters

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