Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment

Abstract

This brief presents a logic synthesis flow that depends on the popular Synopsys Design Compiler to perform logic translation and minimization based on the standard cell library with both pass transistor logic (PTL) and CMOS logic cells. The hybrid PTL/CMOS logic synthesis can generate appropriate circuits considering various design constraints. The proposed multilevel PTL logic cells are automatically constructed from only a few basic cells. Postlayout simulations with UMC 90-nm technology are presented based on the standard cell library with pure PTL, pure CMOS, or hybrid PTL/CMOS cells. Experimental results show that, in most cases, pure PTL circuits have smaller area and power, whereas CMOS circuits, in general, have smaller delay. Index Terms-Cell-based design, LEAn Pas-transistor (LEAP), logic synthesis, pass transistor logic (PTL), standard cell library.

Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic

“…Pass transistor logic (PTL) style is considered to be better than CMOS logic style because it makes use of less number of gates thereby resulting in less delay and hence less power dissipation [3], [4], [5], [6], [7].Restoring logic is required to obtain full swing output thereby resulting in increase in the power dissipation of the circuit. As CMOS and PTL have their respective merits and demerits therefore a combination of both that is HYBRID PTL/CMOS would give best results in terms of power, area, PDP.…”

“…As CMOS and PTL have their respective merits and demerits therefore a combination of both that is HYBRID PTL/CMOS would give best results in terms of power, area, PDP. Logic functions in Hybrid PTL/CMOS are represented through BDD (Binary Decision Diagram) [5], [6].…”

Low-Cost Design of Serial-Parallel Multipliers Over GF(2^m) Using Hybrid Pass-Transistor Logic (PTL) and CMOS Logic

“…The finite field multiplication is performed in two stages of recursive operations, where modular reduction is performed according to (6) in the first stage, and AND-accumulate is performed according to (3) and (4) in the second stage. Fig.…”

“…Although CMOS has been the mainstream logic design style for standard cell library, it has been shown in the past two decades that pass transistor logic (PTL) is an attractive design alternative to CMOS logic in circuit designs involving arithmetic operations or other XOR-rich applications [3][4][5][6]. Recently, hybrid PTL/CMOS synthesis based on Synopsys Design Compiler with both PTL and CMOS standard cell library has been shown to achieve promising results for designing combinational logic circuits [6].…”

“…Recently, hybrid PTL/CMOS synthesis based on Synopsys Design Compiler with both PTL and CMOS standard cell library has been shown to achieve promising results for designing combinational logic circuits [6]. In this paper, we present the PTL circuit designs for the fundamental sequential logic circuits, e.g., D-FF and T-FF, to be used in the design of finite field multiplication over GF (2 m ).…”