Low-area on-chip circuit for jitter measurement in a phase-locked loop

Cazeaux, J.M.; Omana, M.; Metra, C.

doi:10.1109/olt.2004.1319654

Cited by 6 publications

(1 citation statement)

References 11 publications

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“…Since 14 < k < 24 was recommended above, k is set to 16 for the CDNL test. Figure 10 shows the histogram of f CDNL 16 for a total of 2 14 Figure 11 shows the measured results made with 2 22 samples. The gain error is −0.00208LSB and σ DNL = 0.1199 LSB.…”

Section: Resultsmentioning

confidence: 99%

Cumulative Differential Nonlinearity Testing of ADCs

Chen

2012

IEICE Trans. Fundamentals

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This paper proposes a cumulative DNL (CDNL) test methodology for the BIST of ADCs. It analyzes the histogram of the DNL of a predetermined k LSBs distance to determine the DNL and gain error. The advantage of this method over others is that the numbers of required code bins and required samples are significantly reduced. The simulation and measurements of a 12-bit ADC show that the proposed CDNL has an error of less than 5% with only 2 12 samples, which can only be achieved with 2 22 samples using the conventional method. It only needs 16 registers to store code bins in this experiment.

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Section: Resultsmentioning

confidence: 99%

Cumulative Differential Nonlinearity Testing of ADCs

Chen

2012

IEICE Trans. Fundamentals

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A Digital BIST for Phase-Locked Loops

Sliech

Margala

2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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A Novel Jitter Measurement Method with Built-In Oscillation Test Structure for Phase Locked Loops

Xia

Chen²,

Jia³

2005 IEEE Conference on Electron Devices and Solid-State Circuits

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A built-in oscillation test method for jitter measurement of Phase Locked Loops (PLLs) is proposed in this paper. Compared to previous jitter measurement methods, it offers the advantages of two methods of jitter measurement, namely, the one using time-to-voltage converter (TVC) and the other using time-to-digital converter (TDC). Meantime, it utilizes the idea of oscillation built-in self test (OBIST). In this paper, a mathematic model of this method is first proposed, and its principle is explained in detail. Then a custom IC was designed in a 0.18-pm CMOS process as a proof of the concept. This circuit requires a silicon area of 95 pm2 and the simulation results indicate a timing resolution of 10.2 ps. As test time is another important consideration for a production test, the proposed method reduces test time to the theoretical minimum.

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Low-area on-chip circuit for jitter measurement in a phase-locked loop

Cited by 6 publications

References 11 publications

Cumulative Differential Nonlinearity Testing of ADCs

Cumulative Differential Nonlinearity Testing of ADCs

A Digital BIST for Phase-Locked Loops

A Novel Jitter Measurement Method with Built-In Oscillation Test Structure for Phase Locked Loops

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