A Novel Jitter Measurement Method with Built-In Oscillation Test Structure for Phase Locked Loops

Abstract

A built-in oscillation test method for jitter measurement of Phase Locked Loops (PLLs) is proposed in this paper. Compared to previous jitter measurement methods, it offers the advantages of two methods of jitter measurement, namely, the one using time-to-voltage converter (TVC) and the other using time-to-digital converter (TDC). Meantime, it utilizes the idea of oscillation built-in self test (OBIST). In this paper, a mathematic model of this method is first proposed, and its principle is explained in detail. Then a custom IC was designed in a 0.18-pm CMOS process as a proof of the concept. This circuit requires a silicon area of 95 pm2 and the simulation results indicate a timing resolution of 10.2 ps. As test time is another important consideration for a production test, the proposed method reduces test time to the theoretical minimum.