Low area FPGA implementation of PRESENT cryptography with 3S-RLKG and MKS

Tappari, Sunitha

doi:10.1007/s11276-021-02797-7

Cited by 4 publications

(3 citation statements)

References 28 publications

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“…Tappari proposed designing the internal logic circuit of FPGA and creating the firmware program of FX3. It realizes the receiving and storage of LVDS energy data and the reading of energy data in memory by computer [7]. Kowalczyk et al proposed using multiple hard disks to form a RAID array (cheap redundant disk array).…”

Section: Literature Reviewmentioning

confidence: 99%

Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

Luan

2022

International Transactions on Electrical Energy Systems

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In order to solve the problems of small signal acquisition range and poor acquisition accuracy of the existing multichannel acquisition system, a multisensor energy data fusion transformer acquisition system simulation method based on FPGA is proposed, and key hardware functions are designed and implemented. The system uses FPGA to control the core logic, synchronously collects and controls the energy data of the CCD camera and the laser rangefinder, organizes and uses an external large-capacity SDRAM group for buffering, and uses a dedicated PCI interface chip PLX9656 to achieve high-speed data transmission. Two pieces of sensor energy data and PCI bus energy data are stored in real time using a large-capacity disk array composed of multiple SATA hard disks. The function and performance of the energy data acquisition and storage system were tested. After the actual system test, the experimental results show that the transmission speed of the system through the PCI bus exceeds 200 MB/s, the writing speed of the continuous disk array is 240 MB/s, and the real-time acquisition and recording speed is 100 MB/ss. Conclusion. The system effectively solves the problems of high-speed data acquisition and storage and large capacity data transmission of key sensor nodes.

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Section: Literature Reviewmentioning

confidence: 99%

Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

Luan

2022

International Transactions on Electrical Energy Systems

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“…In the DFT field, it requires the random number generator is capable of achieving a high throughput with an excellent randomness. In the prior research works, 37,38 PRESENT cryptographic circuits were tailored to study the effectiveness of generating random numbers for DFT to test the faults of integrated circuits. However, these prior works mainly aim at improving the randomness of the generated random numbers without fully optimizing the overall design cost.…”

Section: Future Workmentioning

confidence: 99%

A high‐speed and low‐latency hardware implementation of RC4 cryptographic algorithm

Sun,

Liu,

Cheng

et al. 2023

Circuit Theory & Apps

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In this letter, a high‐speed and low‐latency Ron Rivest‐4 (RC4) encryption algorithm is designed based on SMIC 14 nm process. Since the key issue of limiting the throughput of RC4 encryption algorithm is the swapping operation of S‐box, this proposed design is capable of achieving four swapping operations of S‐box within a clock cycle by utilizing fully combinational logic designs and advanced computations. All 256 swapping operations of key scheduling algorithm (KSA) can be done in 64 clock cycles. Moreover, the novel design greatly improves the encryption efficiency of RC4 since each clock cycle offers 4 bytes of key stream. The whole area can be further optimized by reusing the existing modules, and a lightweight countermeasure is embedded into the RC4 design to break the correlation between the processed data and power dissipation against differential power analysis (DPA) attacks. Finally, the whole design is assessed by the SMIC 14 nm process design kits (PDK). The corresponding clock frequency, throughput, area, and latency, respectively, are achieved as 1 GHz, 32 Gbps, 51,596 m2, and 74 clock cycles.

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“…To solve this problem, many lightweight cryptography algorithms have emerged in recent years. The algorithm PRESENT published in 2007 tries to replace AES in some IoT devices 8,9 . The evaluation results show that this algorithm achieves good security with resources far fewer than AES.…”

Section: Introductionmentioning

confidence: 99%

Lightweight and flexible hardware implementation of authenticated encryption algorithm SIMON‐Galois/Counter Mode

Cheng

Wang

et al. 2023

Circuit Theory & Apps

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SummaryThis brief proposes a new lightweight authenticated encryption algorithm SIMON‐GCM for Internet of Things (IoT) security, which realizes the combination of SIMON block cipher and Galois/Counter Mode (GCM). The designed SIMON circuit supports 128/192/256‐bit key size, which improves the flexibility and enlarges the range of applications. Moreover, the scheme of 32‐cycle Galois field (GF) multiplier in GF(2128) is adopted to effectively reduce the hardware cost of the Galois Hash (GHASH) function in GCM. At the same time, a finite state machine (FSM) is used to run the SIMON and GHASH modules in parallel, thus shortening the authenticated encryption time. The whole circuit is designed and implemented in field programmable gate array (FPGA) platforms. It is measured to yield a throughput of 32.4 Gbps when consuming 331 slices in Artix‐7. Compared with the existing authenticated encryption algorithms, the proposed algorithm achieves lower resource consumption and better flexibility.

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Low area FPGA implementation of PRESENT cryptography with 3S-RLKG and MKS

Cited by 4 publications

References 28 publications

Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

A high‐speed and low‐latency hardware implementation of RC4 cryptographic algorithm

Lightweight and flexible hardware implementation of authenticated encryption algorithm SIMON‐Galois/Counter Mode

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